Asymmetrical processor memory architecture
An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.
1. An asymmetrical processing system comprising:
a scalar unit having a single memory port;
a vector unit comprised of one or more computational units coupled with a vector memory space;
wherein the vector memory space includes a first memory port coupled to exchange data with the memory port of the scalar unit, and a second memory port coupled to exchange data with the computational units;
a data memory space having a memory port and contiguous with the vector memory space;
wherein the memory port of the data memory space is coupled to exchange data with the memory port of the scalar unit; and
wherein the scalar unit is configured to directly address and exchange data with both the data memory space and the vector memory space through the single memory port of the scalar unit.
2. The processing system according to claim 1 ,
wherein the scalar unit accesses the data memory space and vector memory space concurrently.
3. The processing system according to claim 1 ,
wherein the scalar unit accesses the data memory space and the one or more computational units access the vector memory space concurrently.
4. The processing system according to claim 1 , further comprising:
a program memory space storing instructions for the scalar unit and vector unit; and
instruction decode logic for decoding an instruction retrieved from the program memory space.
5. The processing system according to claim 4 ,
wherein the scalar unit and the vector unit operate on a decoded instruction in parallel.
6. The processing system according to claim 5 , further comprising a configurable memory access mode to determine a slice or a column memory access mode.
7. The processing system according to claim 6 ,
wherein the access mode is determined by access bits or register bits.
8. The processing system according to claim 2 ,
wherein the scalar unit accesses the vector memory in slice mode sequentially across a plurality of vector memory locations each associated with one of the one or more computational units.
9. The processing system according to claim 7 ,
wherein the scalar unit accesses the vector memory consecutively in column mode wherein a vector memory location associated with one of the one or more computational units is accessed.
10. The processing system according to claim 9 ,
wherein the vector memory is divided into a plurality of sub-blocks allowing the scalar unit to access the sub-blocks concurrently.
11. The processing system according to claim 10 ,
wherein only a portion of the vector memory is accessible by the scalar unit.
12. The processing system according to claim 11 ,
wherein the portion of vector memory is defined by a predetermined threshold.
13. The processing system according to claim 12 ,
wherein the scalar unit accesses the data memory space and a plurality of vector memory space concurrently.
14. The processing system according to claim 13 ,
wherein the scalar unit accesses the data memory space, a plurality of vector memory space, and the one or more computational units access the vector memory space.
15. The processing system according to claim 14 ,
wherein the vector memory space is allocated in software.
16. The processing system according to claim 1 ,
wherein the vector memory space is hard coded.
17. The processing system according to claim 15 ,
wherein the memory access method is determined at start up of the processing system.