Silicon carbide semiconductor device and method for manufacturing the same
A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region. The first connection region is provided to include a first intersection and a second intersection, the first intersection being an intersection of a straight line along a first straight-line portion and a straight line along a second straight-line portion, the second intersection being an intersection of a straight line along a third straight-line portion and a straight line along a fourth straight-line portion, and the first connection region has a second conductivity type.
1. A silicon carbide semiconductor device, comprising:
a silicon carbide substrate having a first main surface and a second main surface opposite to said first main surface; and
a gate electrode provided on a side of said first main surface of said silicon carbide substrate, wherein
said silicon carbide substrate includes
a first source region and a second source region which are adjacent to each other and have an outer shape that is a polygon when viewed in a plan view, and have a first conductivity type,
a first body region which is formed to surround said first source region when viewed in a plan view, and has a second conductivity type,
a second body region which is formed to surround said second source region when viewed in a plan view, and has said second conductivity type,
a first drift region which is sandwiched between said first body region and said second body region, is separated from said first source region by said first body region, is separated from said second source region by said second body region, and has said first conductivity type,
a second drift region which is in contact with said second body region, is separated from said second source region by said second body region, and has said first conductivity type, and
a third drift region which is in contact with said first body region, is separated from said first source region by said first body region, and has said first conductivity type,
said first body region having a first straight-line portion which is in contact with said first drift region, and a second straight-line portion which is located adjacent to said first straight-line portion and is in contact with said third drift region when viewed in a plan view,
said second body region having a third straight-line portion which is in contact with said first drift region, and a fourth straight-line portion which is located adjacent to said third straight-line portion, on a side close to said second straight-line portion, and is in contact with said second drift region when viewed in a plan view,
said silicon carbide substrate further includes a first connection region provided to include a first intersection and a second intersection, said first intersection being an intersection of a straight line along said first straight-line portion and a straight line along said second straight-line portion, said second intersection being an intersection of a straight line along said third straight-line portion and a straight line along said fourth straight-line portion, said first connection region having said second conductivity type, and
said gate electrode is provided to overlap said first body region sandwiched between said first source region and said first drift region, said second body region sandwiched between said second source region and said first drift region, and said first connection region, when viewed in a plan view,
said first body region further has a fifth straight-line portion which is located adjacent to said first straight-line portion, on a side opposite to said second straight-line portion, and constitutes an outer periphery of said first body region, when viewed in a plan view,
said second body region further has a sixth straight-line portion which is located adjacent to said third straight-line portion, on a side opposite to said fourth straight-line portion, and constitutes an outer periphery of said second body region, when viewed in a plan view,
said silicon carbide substrate includes a second connection region provided to include a third intersection and a fourth intersection, said third intersection being an intersection of the straight line along said first straight-line portion and a straight line along said fifth straight-line portion, said fourth intersection being an intersection of the straight line along said third straight-line portion and a straight line along said sixth straight-line portion, said second connection region having said second conductivity type, and
a relation B>0.5×A is satisfied, where A represents a distance from the center of said first connection region to the center of said second connection region, and B represents a minimum distance between said first connection region and said second connection region, when viewed in a plan view.
2. The silicon carbide semiconductor device according to claim 1 , wherein said polygon is a hexagon.
3. The silicon carbide semiconductor device according to claim 2 , wherein said first connection region has a shape that is a triangle when viewed in a plan view.
4. The silicon carbide semiconductor device according to claim 2 , wherein
said silicon carbide substrate further includes
a third source region which is located adjacent to said first source region and said second source region and has an outer shape that is a hexagon when viewed in a plan view, and has the first conductivity type, and
a third body region which is formed to surround said third source region when viewed in a plan view, and has said second conductivity type,
said second drift region is sandwiched between said second body region and said third body region, and is separated from said third source region by said third body region,
said third drift region is sandwiched between said first body region and said third body region, and is separated from said first source region by said first body region, and
said first connection region is provided to be surrounded by said first body region, said second body region, said third body region, said first drift region, said second drift region, and said third drift region when viewed in a plan view.
5. The silicon carbide semiconductor device according to claim 1 , wherein said first connection region has an impurity concentration of more than or equal to 1×10 16 cm −3 and less than or equal to 1×10 20 cm −3 .
6. The silicon carbide semiconductor device according to claim 5 , wherein said first connection region has an impurity concentration of less than or equal to 1×10 19 cm −3 .
7. The silicon carbide semiconductor device according to claim 1 , wherein a thickness of said first connection region along a direction of a normal to said first main surface is less than or equal to a thickness of each of said first body region and said second body region.
8. The silicon carbide semiconductor device according to claim 1 , further comprising:
a first contact region which is surrounded by said first source region when viewed in a plan view and has the second conductivity type; and
a second contact region which is surrounded by said second source region when viewed in a plan view and has the second conductivity type, wherein
said first connection region has an impurity concentration identical to that of each of said first contact region and said second contact region.
9. The silicon carbide semiconductor device according to claim 1 , wherein said first connection region has an impurity concentration identical to that of each of said first body region and said second body region.
10. The silicon carbide semiconductor device according to claim 1 , further comprising a gate oxide film provided to be sandwiched between said gate electrode and each of said first connection region, said first body region, and said second body region, wherein
a thickness of said gate oxide film on said first connection region is larger than a thickness of said gate oxide film on each of said first body region and said second body region.
11. The silicon carbide semiconductor device according to claim 1 , wherein said first conductivity type is n type, and said second conductivity type is p type.
12. A method for manufacturing a silicon carbide semiconductor device, comprising steps of:
preparing a silicon carbide substrate having a first main surface and a second main surface opposite to said first main surface; and
forming a gate electrode on a side of said first main surface of said silicon carbide substrate,
said silicon carbide substrate includes
a first source region and a second source region which are adjacent to each other and have an outer shape that is a polygon when viewed in a plan view, and have a first conductivity type,
a first body region which is formed to surround said first source region when viewed in a plan view, and has a second conductivity type,
a second body region which is formed to surround said second source region when viewed in a plan view, and has said second conductivity type,
a first drift region which is sandwiched between said first body region and said second body region, is separated from said first source region by said first body region, is separated from said second source region by said second body region, and has said first conductivity type,
a second drift region which is in contact with said second body region, is separated from said second source region by said second body region, and has said first conductivity type, and
a third drift region which is in contact with said first body region, is separated from said first source region by said first body region, and has said first conductivity type,
said first body region having a first straight-line portion which is in contact with said first drift region, and a second straight-line portion which is located adjacent to said first straight-line portion and is in contact with said third drift region when viewed in a plan view,
said second body region having a third straight-line portion which is in contact with said first drift region, and a fourth straight-line portion which is located adjacent to said third straight-line portion, on a side close to said second straight-line portion, and is in contact with said second drift region when viewed in a plan view,
said silicon carbide substrate further includes a first connection region provided to include a first intersection and a second intersection, said first intersection being an intersection of a straight line along said first straight-line portion and a straight line along said second straight-line portion, said second intersection being an intersection of a straight line along said third straight-line portion and a straight line along said fourth straight-line portion, said first connection region having said second conductivity type, and
in the step of forming said gate electrode, said gate electrode is formed to overlap said first body region sandwiched between said first source region and said first drift region, said second body region sandwiched between said second source region and said first drift region, and said first connection region, when viewed in a plan view,
said first body region further has a fifth straight-line portion which is located adjacent to said first straight-line portion, on a side opposite to said second straight-line portion, and constitutes an outer periphery of said first body region, when viewed in a plan view,
said second body region further has a sixth straight-line portion which is located adjacent to said third straight-line portion, on a side opposite to said fourth straight-line portion, and constitutes an outer periphery of said second body region, when viewed in a plan view,
said silicon carbide substrate includes a second connection region provided to include a third intersection and a fourth intersection, said third intersection being an intersection of the straight line along said first straight-line portion and a straight line along said fifth straight-line portion, said fourth intersection being an intersection of the straight line along said third straight-line portion and a straight line along said sixth straight-line portion, said second connection region having said second conductivity type, and
a relation B>0.5×A is satisfied, where A represents a distance from the center of said first connection region to the center of said second connection region, and B represents a minimum distance between said first connection region and said second connection region, when viewed in a plan view.
13. The method for manufacturing the silicon carbide semiconductor device according to claim 12 , wherein the step of preparing said silicon carbide substrate includes a step of simultaneously forming said first connection region, said first body region, and said second body region.
14. The method for manufacturing the silicon carbide semiconductor device according to claim 13 , wherein
the step of preparing said silicon carbide substrate includes a step of forming a first mask layer on said first main surface of said silicon carbide substrate,
said first connection region, said first body region, and said second body region are formed using said first mask layer, and
the step of preparing said silicon carbide substrate further includes steps of
removing said first mask layer,
forming a second mask layer on said first main surface of said silicon carbide substrate, and
forming said first source region and said second source region using said second mask layer.
15. The method for manufacturing the silicon carbide semiconductor device according to claim 12 , wherein
said silicon carbide substrate further includes a first contact region which is surrounded by said first source region when viewed in a plan view and has the second conductivity type, and a second contact region which is surrounded by said second source region when viewed in a plan view and has the second conductivity type, and
the step of preparing said silicon carbide substrate includes a step of simultaneously forming said first connection region, said first contact region, and said second contact region.
16. The method for manufacturing the silicon carbide semiconductor device according to claim 15 , wherein
the step of preparing said silicon carbide substrate further includes steps of
forming a first mask layer on said first main surface of said silicon carbide substrate,
forming a second mask layer which is in contact with said first mask layer on said silicon carbide substrate, and
forming said first source region and said second source region using said first mask layer and said second mask layer, and
the step of simultaneously forming said first connection region, said first contact region, and said second contact region is performed after the step of forming said first source region and said second source region.
17. The method for manufacturing the silicon carbide semiconductor device according to claim 12 , further comprising a step of forming a gate oxide film which is in contact with each of said first connection region, said first body region, and said second body region, wherein
the step of forming said gate oxide film includes steps of
forming a silicon dioxide layer or a polysilicon layer on said first connection region of said silicon carbide substrate, and
performing thermal oxidation on said first main surface of said silicon carbide substrate having said silicon dioxide layer or said polysilicon layer formed thereon.