Sense amplifiers and multiplexed latches
View Patent ↗Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.
1. A multiplexed latch comprising:
a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output;
a first latch having a first latch clock input, and a first latch output;
a second latch having a second latch clock input, and a second latch output; and
a feedback loop connecting the multiplexor output to the first latch clock input and the second latch clock input,
the first latch output being connected to the first data input of the multiplexor,
the second latch output being connected to the second data input of the multiplexor,
when the selection input of the multiplexor receives a first latch selection signal, the feedback loop forces the first latch output to remain unchanged until the first latch clock input transitions, and
when the selection input of the multiplexor receives a second latch selection signal, the feedback loop forces the second latch output to remain unchanged until the second latch clock input transitions.
2. The multiplexed latch according to claim 1 , the first latch clock input comprising a first gate passing signals from the multiplexor output, the first gate being controlled by a complement clock signal that is complementary to a clock signal, and
the second latch clock input comprising a second gate passing the signals from the multiplexor output, the second gate being controlled by the complement clock signal.
3. The multiplexed latch according to claim 2 , the first gate passing the signals from the multiplexor output to the first latch output, and
the second gate passing the signals from the multiplexor output to the second latch output.
4. The multiplexed latch according to claim 1 , the first latch and the second latch comprising NOR latches.
5. The multiplexed latch according to claim 1 , the first latch and the second latch comprising sense amplifier drivers.
6. The multiplexed latch according to claim 1 , the first latch output providing read global bitline true (RGBLT) signals and the second latch output providing read global bitline complement signals (RGBLC).
7. The multiplexed latch according to claim 1 , the first latch selection signal and the second latch selection signal comprising replica cell array (RCA) memory address signals.
8. An electronic memory device comprising:
memory cells;
a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output;
a first sense amplifier latch connected to the memory cells, the first sense amplifier latch having a first sense amplifier latch clock complement input, and a first sense amplifier latch output;
a second sense amplifier latch connected to a second sense amplifier of the sense amplifiers, the second sense amplifier latch having a second sense amplifier latch clock complement input, and a second sense amplifier latch output; and
a feedback loop connecting the multiplexor output to the first sense amplifier latch and the second sense amplifier latch,
the first sense amplifier latch output being connected to the first data input of the multiplexor,
the second sense amplifier latch output being connected to the second data input of the multiplexor,
the selection input of the multiplexor receiving either a first sense amplifier latch selection signal or a second sense amplifier latch selection signal,
while the selection input of the multiplexor receives the first sense amplifier latch selection signal, the feedback loop forces the first sense amplifier latch output to remain unchanged until the first sense amplifier latch clock complement input transitions, and
while the selection input of the multiplexor receives the second sense amplifier latch selection signal, the feedback loop forces the second sense amplifier latch output to remain unchanged until the second sense amplifier latch clock complement input transitions.
9. The electronic memory device according to claim 8 , the first sense amplifier latch clock complement input comprising a first inverter passing signals from the multiplexor output, the first inverter being controlled by a complement clock signal that is complementary to a clock signal, and
the second sense amplifier latch clock complement input comprising a second inverter passing the signals from the multiplexor output, the second inverter being controlled by the complement clock signal.
10. The electronic memory device according to claim 9 , the first inverter passing the signals from the multiplexor output to the first sense amplifier latch output, and
the second inverter passing the signals from the multiplexor output to the second sense amplifier latch output.
11. The electronic memory device according to claim 8 , the first sense amplifier latch and the second sense amplifier latch comprising NOR latches.
12. The electronic memory device according to claim 8 , the first sense amplifier latch and the second sense amplifier latch comprising operational amplifier drivers.
13. The electronic memory device according to claim 8 , the first sense amplifier latch output providing read global bitline true (RGBLT) signals and the second sense amplifier latch output providing read global bitline complement signals (RGBLC).
14. The electronic memory device according to claim 8 , the first sense amplifier latch selection signal and the second sense amplifier latch selection signal comprising replica cell array (RCA) memory address signals.
15. An electronic memory device comprising:
memory cells; and
multiplexed latches connected to the memory cells, each of the multiplexed latches comprising:
a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output;
a first sense amplifier latch selectively connected by switches to the multiplexor, the first sense amplifier latch having a first sense amplifier latch clock complement input, and a first sense amplifier latch output;
a second sense amplifier latch selectively connected by switches to the multiplexor, the second sense amplifier latch having a second sense amplifier latch clock complement input, and a second sense amplifier latch output;
a redundant latch selectively connected by switches to the multiplexor, the redundant latch having a redundant latch clock complement input, and a redundant latch output; and
a feedback loop connecting the multiplexor output to the first sense amplifier latch, the second sense amplifier latch, and the redundant latch,
the switches connecting only two of the first sense amplifier latch, the second sense amplifier latch, and the redundant latch to the multiplexor output at a time,
depending upon settings of the switches, two of: the first sense amplifier latch output; the second sense amplifier latch output; and the redundant latch output being connected to the first data input and the second data input of the multiplexor,
the selection input of the multiplexor receiving either a first sense amplifier latch selection signal or a second sense amplifier latch selection signal,
while the selection input of the multiplexor receives the first sense amplifier latch selection signal, the feedback loop forces the first sense amplifier latch output to remain unchanged until the first sense amplifier latch clock complement input transitions to a first different clock state that is different from a first previous clock state that was present before the multiplexor received the first sense amplifier latch selection signal, and
while the selection input of the multiplexor receives the second sense amplifier latch selection signal, the feedback loop forces the second sense amplifier latch output to remain unchanged until the second sense amplifier latch clock complement input transitions to a second different clock state that is different from a second previous clock state that was present before the multiplexor received the second sense amplifier latch selection signal.
16. The electronic memory device according to claim 15 , the first sense amplifier latch clock complement input comprising a first inverter passing signals from the multiplexor output, the first inverter being controlled by a complement clock signal that is complementary to a clock signal, and
the second sense amplifier latch clock complement input comprising a second inverter passing the signals from the multiplexor output, the second inverter being controlled by the complement clock signal.
17. The electronic memory device according to claim 16 , the first inverter passing the signals from the multiplexor output to the first sense amplifier latch output, and
the second inverter passing the signals from the multiplexor output to the second sense amplifier latch output.
18. The electronic memory device according to claim 15 , the first sense amplifier latch and the second sense amplifier latch comprising NOR latches.
19. The electronic memory device according to claim 15 , the first sense amplifier latch and the second sense amplifier latch comprising operational amplifier drivers.
20. The electronic memory device according to claim 15 , the first sense amplifier latch output providing read global bitline true (RGBLT) signals and the second sense amplifier latch output providing read global bitline complement signals (RGBLC).