Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping

1. A method of forming semiconductor devices comprising:

forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension;

diffusing the punch through dopant from the oxide into the semiconductor material to provide a punch through stop region;

removing the oxide;

forming a second semiconductor material having a second lattice dimension on the first semiconductor material having the first lattice dimension, wherein a difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material;

etching the second semiconductor material provide a fin structure after forming the punch through stop region, wherein a channel region of the fin structure being in direct contact with the punch through stop region; and

forming a gate structure and source and drain regions on the second semiconductor material after forming the fin structure.

2. The method of claim 1 , wherein the second semiconductor material has a larger lattice dimension than the first semiconductor material, and the strain in the second semiconductor material is compressive.

3. The method of claim 2 , wherein the punch through dopant is n-type, and the source and drain regions are p-type.

4. The method of claim 1 , wherein the second semiconductor material has a smaller lattice dimension than the first semiconductor material, and the strain in the second semiconductor material is tensile.

5. The method of claim 4 , wherein the punch through dopant is p-type and the source and drain regions are n-type.

6. A method of forming a semiconductor device comprising:

forming a first doped oxide having a first conductivity type dopant on a first region of a semiconductor substrate having a first lattice dimension, and forming a second doped oxide having a second conductivity type dopant on a second region of the semiconductor substrate;

diffusing the first and second conductivity type dopants from the first and second doped oxides into the first and second region of the semiconductor substrate, wherein the first conductivity type dopant that diffuses into the first region of the substrate provides a first conductivity type punch through stop region, and the second conductivity type dopant that diffuses into the second region of the substrate provides a second conductivity type punch through stop region;

removing the first and second doped oxides;

forming at least a second semiconductor material having at least a second lattice dimension on the semiconductor substrate, wherein a difference between the first lattice dimensions and at least the second lattice dimension forms a strain in said at least said second semiconductor material layer

forming fin structures in the first and second regions of the semiconductor substrate from said at least the second semiconductor material after forming said first conductivity type punch through stop region and second conductivity type punch through stop region, wherein channel regions of the fin structures are in direct contact with the first conductivity type and the second conductivity type punch through stop regions;

forming a first semiconductor device having a second conductivity type on the fin structure in the first region of the semiconductor substrate; and

forming a second semiconductor device having a first conductivity type on the fin structure in the second region of the semiconductor substrate.

7. The method of claim 6 , wherein said semiconductor substrate comprises a relaxed semiconductor layer atop a bulk semiconductor substrate.

8. The method of claim 6 , wherein said forming the first doped oxide having said first conductivity type dopant on the first region of the semiconductor substrate and said forming a second doped oxide having said second conductivity type dopant on said second region of the semiconductor substrate comprises:

depositing said first doped oxide on an entirety of said semiconductor substrate;

depositing a first hard mask layer on said first doped oxide;

patterning a stack of said first hard mask layer and said first doped oxide to be present only in said first region of the semiconductor substrate, wherein said second region of the semiconductor substrate is exposed;

depositing a second doped oxide on at least the second region of the semiconductor substrate; and

depositing a second hard mask layer atop the second doped oxide.

9. The method of claim 6 , wherein diffusing the first and second conductivity type dopants for the first and second doped oxides into the first and second region of the semiconductor substrate comprises thermal annealing.

10. The method of claim 8 , wherein removing the first and second doped oxides comprises a strip process that also removes the first and second hard masks.

11. The method of claim 6 , wherein forming said at least a second semiconductor material having at least a second lattice dimension comprises:

forming said second semiconductor material having a larger lattice dimension than the first semiconductor material on the second region of the substrate, and the strain in the second semiconductor material being compressive; and

forming a third semiconductor material having a lesser lattice dimension than the first semiconductor material on the first region of the substrate, the strain in the third semiconductor material being tensile.

12. The method of claim 11 , further comprising forming a gate structure on a channel region of each of the fin structures, and forming source and drain regions on opposing sides of the channel region for the fin structures.

13. The method of claim 12 , wherein the first conductivity type punch through stop region dopant is n-type, and the source and drain regions of the first semiconductor device are p-type.

14. The method of claim 12 , wherein the second conductivity type punch through stop region dopant is p-type, and the source and drain regions of the second semiconductor device are n-type.