Packaging substrate with block-type via and semiconductor packages having the same
A packaging substrate includes a core layer having a first surface and a second surface. A group of ground pads is disposed on the second surface within a central region. A group of first power pads is disposed on the second surface within the central region. A plurality of signal pads is disposed on the second surface within a peripheral region that encircles the central region on the second surface. A first block-type via is embedded in the core layer within the central region. The group of ground pads is electrically connected to the first block-type via. A second block-type via is embedded in the core layer within the central region. The group of first power pads is electrically connected to the second block-type via.
1. A packaging substrate, comprising:
a layer of a core layer material, having a first surface and a second surface being opposite to the first surface;
a central region on the second surface;
a peripheral region encircling the central region;
a group of ground pads disposed on the second surface within the central region;
a group of first power pads disposed on the second surface within the central region;
a group of second power pads disposed on the second surface within the central region;
a plurality of signal pads disposed on the second surface within the peripheral region;
a single first block-type via embedded in the layer within the central region, wherein the group of ground pads is physically in contact with the single first block-type via;
a single second block-type via embedded in the layer within the central region, wherein the group of first power pads is physically in contact with the single second block-type via, and the single first block-type via completely surrounds the single second block-type via; and
a third block-type via embedded in the core layer within the central region, wherein the group of second power pads is electrically connected to the third block-type via,
wherein a first portion of the core layer material separates the single first block-type via and single second block-type via, a second portion of the core layer material is outside the single first block-type via, and the first and second portions of the core layer material have a same dielectric constant, and
wherein the single first block-type via has a finger separating the single second block-type via and third block-type via.
2. The packaging substrate according to claim 1 , wherein the single first block-type via and the single second block-type via are made of monolithic metal that penetrates through an entire thickness of the layer of the core layer material.
3. The packaging substrate according to claim 1 , wherein the core layer material comprises prepreg or fiberglass-epoxy resin.
4. The packaging substrate according to claim 1 , wherein the group of ground pads communicates with the first surface only through the single first block-type via.
5. The packaging substrate according to claim 1 , wherein the group of first power pads communicates with the first surface only through the single second block-type via.
6. The packaging substrate according to claim 1 , wherein the group of first power pads is used to convey a power signal in a first power domain, and the group of second power pads is used to convey a power signal in a second power domain that is different from the first power domain.
7. The packaging substrate according to claim 6 , wherein the power signal in a first power domain is V CC and the power signal in a second power domain is V DD .
8. The packaging substrate according to claim 1 , wherein the ground pads and the first power pads are copper pads.
9. The packaging substrate according to claim 1 , wherein the single first block-type via and the single second block-type via comprise copper.
10. The packaging substrate according to claim 1 , wherein the signal pads within the peripheral region communicate with the first surface through plated through holes respectively.
11. A flip chip chip-scale package, comprising:
a packaging substrate according to claim 1 ; and
a flipped chip facedown assembled on the first surface of the packaging substrate, wherein the group of ground pads communicates with the first surface only through the single first block-type via.
12. A flip chip chip-scale package, comprising:
a packaging substrate according to claim 1 ; and
a flipped chip facedown assembled on the first surface of the packaging substrate, wherein the group of first power pads communicates with the first surface only through the single second block-type via.
13. A package-on-package, comprising:
a packaging substrate according to claim 1 ;
a flipped chip facedown assembled on the first surface of the packaging substrate; and
a chip package assembled on the first surface of the packaging substrate.
14. The package-on-package according to claim 13 , wherein the chip package comprises a DRAM chip package.
15. The package-on-package according to claim 13 , wherein the group of ground pads communicates with the first surface only through the single first block-type via.
16. The package-on-package according to claim 13 , wherein the group of first power pads communicates with the first surface only through the single second block-type via.
17. The package-on-package according to claim 13 further comprising:
a group of second power pads disposed on the second surface within the central region; and
a third block-type via embedded in the layer of the core layer material within the central region, wherein the group of second power pads is electrically connected to the third block-type via.
18. The package-on-package according to claim 17 , wherein the group of first power pads is used to convey a power signal in a first power domain, and the group of second power pads is used to convey a power signal in a second power domain that is different from the first power domain.
19. A packaging substrate, comprising:
a core layer having a first surface and a second surface being opposite to the first surface;
a central region on the second surface;
a peripheral region encircling the central region;
a group of ground pads disposed on the second surface within the central region;
a group of first power pads disposed on the second surface within the central region;
a group of second power pads disposed on the second surface within the central region;
a plurality of signal pads disposed on the second surface within the peripheral region;
a single first block-type via embedded in the core layer within the central region, wherein the group of ground pads is physically in contact with the single first block-type via;
a single second block-type via embedded in the core layer within the central region, wherein the group of first power pads is physically in contact with the single second block-type via; and
a single third block-type via embedded in the core layer within the central region, wherein the group of second power pads is physically in contact with the single third block-type via;
wherein the single first block-type via is all around the single second block-type via and single third block-type via, and the single first block-type via has a finger separating the single second block-type via and single third block-type via.
20. The packaging substrate according to claim 19 , wherein the group of first power pads is used to convey a power signal in a first power domain, and the group of second power pads is used to convey a power signal in a second power domain that is different from the first power domain.