IP Library Granted Patent US 9,874,894
Granted Patent B2
US 9,874,894 · App. 14/936,927 · Granted Jan 23, 2018

Temperature stable reference current

Inventor: Akinobu Onishi (Ota, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G05F3/262
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Quick Facts
Patent No.
US 9,874,894
App. No.
14/936,927
Granted
Jan 23, 2018
Kind
B2
Abstract

A circuit for generating a constant current includes a first current generator that conducts a first current based upon a supply voltage and a resistive element and that generates a first mirrored current based on the current, a second current generator that generates a second current based on the first current wherein the second mirrored current decreases as the current increases and decreases as the current increases and a summing circuit for summing currents proportional to said first and second currents to generate an output current.

Claims (35)

1. A circuit for generating a constant current, comprising:

a first current generator that conducts a first current based upon a supply voltage and a resistive element;

a second current generator that generates a second current based on the first current wherein the second current decreases as the first current increases and increases as the first current decreases;

a summing circuit for summing currents proportional to said first and second currents to generate an output current, wherein the summing circuit comprises:

a first current mirror for providing a first mirrored current proportional to the first current;

a second current mirror for providing a second mirrored current proportional to the second current; and

a summing device for summing the first and second mirrored currents to provide a first reference current, and

a third current mirror for providing a second reference current proportional to the first reference current.

2. The circuit for generating the constant current of claim 1 wherein the second reference current changes approximately 10% or less in relation to changes in the first current due to either loading or circuit temperature changes.

3. The circuit for generating the constant current of claim 1 wherein the first current and a resistance of the resistive element increase with temperature increases.

4. The circuit for generating the constant current of claim 3 wherein the first current and the resistance of the resistive element increase as much as 20% with temperature increases.

5. The circuit for generating the constant current of claim 1 wherein the second reference current changes no more than 2% for a 20% change in the first current due to temperature changes.

6. The circuit for generating the constant current of claim 1 wherein the second mirrored current decreases as a circuit temperature increases.

7. The circuit for generating the constant current of claim 1 wherein the first current mirror uses n-channel MOSFETs and the third current mirror uses p-channel MOSFETs or the first current mirror uses p-channel MOSFETs and the third current mirror uses n-channel MOSFETs.

8. The circuit for generating the constant current of claim 7 wherein the second current mirror uses the same type of MOSFETs as the first current mirror.

9. The circuit for generating the constant current of claim 1 wherein the third current mirror comprises at least two MOSFETs that generate two constant current source outputs based on the sum of the first and second mirrored currents.

10. A system for generating a constant reference current, comprising:

a first current generator configured to generate a first current;

a first current mirror that generates a first mirrored current based on the first current;

a second current generator that generates a second current;

a second current mirror that generates a second mirrored current based on the second current; and

a third current mirror that generates a reference current based on a sum of the first and second mirrored currents.

11. The system of claim 10 wherein the second current generator is configured to decrease a magnitude of the second current based upon at least one of an increase in temperature and an increase in the first current.

12. The system of claim 11 wherein the second current generator decreases the second current based on increases in the first current and, inversely, increases the second current based on decreases in the first current.

13. A method in a circuit configured for generating a substantially constant reference current course, comprising:

generating a first current;

generating a first mirrored current proportional to the first current;

generating a second current based on the first current, wherein the second current decreases as the first current increases and increases as the first current decreases;

generating a second mirrored current proportional to the second current;

generating a first reference current proportional to a sum of the first and second mirrored currents; and

generating a second reference current proportional to the first reference current.

14. The method of claim 13 further including decreasing the second current based upon an increase in temperature.

15. The method of claim 13 further including decreasing the second mirrored current based on increases in the first current and, inversely, increasing the second mirrored current based upon decreases in the first current.

16. The method of claim 13 wherein the reference current changes no more than 10 percent in relation to changes in the first current.

17. The method of claim 13 further including generating the first current based upon a voltage and a current setting resistive element.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2015
From: ONISHI, AKINOBU
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 037000/0428 →
Continuity (2)
Provisional Application 62193462 · Jul 16, 2015
Related Publication 20170017253A1 · Jan 19, 2017