Hybrid SM3 and SHA acceleration processors

1. A processing system comprising:

a processing core; and

a hardware accelerator communicatively coupled to the processing core, the hardware accelerator comprising:

a message scheduling module selectively operating in one of a secure hash algorithm (SHA) mode or an SM3 mode to generate a sequence of message words based on an incoming message;

a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words, wherein the round computation module further comprises:

a first shared circuit to perform at least one of a Maj function in the SHA mode or a FF function in the SM3 mode; and

a second shared circuit to perform at least one of a Ch function in the SHA mode or a GG function in the SM3 mode.

2. The processing system of claim 1 further comprising a control module to select one of the SHA mode or the SM3 mode.

3. The processing system of claim 1 wherein the message scheduling module comprise at least one multiplexer to select the operating in one of the SHA mode or the SM3 mode.

4. The processing system of claim 3 wherein the message scheduling module comprises a plurality of message registers, wherein each of the plurality of the message registers function to operate in one of a load mode and a word-shift mode such that each one of the plurality of the message registers is coupled to other of the plurality of the message registers and at least one of the plurality of the message registers is coupled to the at least one multiplexer.

5. The processing system of claim 4 , wherein the message scheduling module comprises a plurality of logic functions coupled to at least one of the message register among the plurality of message registers to generate the sequence of message words.

6. The processing system of claim 1 wherein the round computation module comprise at least one multiplexer to select the operating in one of the SHA mode or the SM3 mode.

7. The processing system of claim 6 wherein the round computation module comprises a plurality of state registers, wherein each of the plurality of state registers is coupled to the at least one multiplexer and store a current state value based on one of the SHA mode or the SM3 mode.

8. The processing system of claim 7 wherein the round computation module comprise a plurality of logic functions to process the current state in each of the state registers using the sequence of words and a constant value to generate an updated current state, wherein the constant value is a first constant value in the SM3 mode and the constant value is a second constant value in the SHA mode, wherein the first constant value is different from the second constant value.

9. The processing system of claim 1 wherein the sequence of message words comprise a single message word in the SHA mode and wherein the sequence of message words comprise a pair of message words in the SM3 mode, wherein one message word in the pair of message words is the single message word and other message word in the pair of message words is different from the single message word.

10. A system-on-a chip (SoC) comprising:

a memory; and

a processor, communicatively coupled to the memory, comprising:

a processing core; and

a hardware accelerator communicatively coupled to the processing core, the hardware accelerator comprising:

a message scheduling module selectively operating in one of a secure hash algorithm (SHA) mode or an SM3 mode to generate a sequence of message words based on an incoming message; and

a round computation module selectively operating in one of the SHA mode or the SM3 mode to perform at least one of a message expansion or a message compression based on at least one message word of the sequence of message words, wherein the round computation module further comprises:

a first shared circuit to perform at least one of a Maj function in the SHA mode or a FF function in the SM3 mode; and

a second shared circuit to perform at least one of a Ch function in the SHA mode or a GG function in the SM3 mode.

11. The SoC of claim 10 further comprising a control module to select one of the SHA mode or the SM3 mode.

12. The SoC of claim 10 wherein the message scheduling module comprise at least one multiplexer to select the operating in one of the SHA mode or the SM3 mode.

13. The SoC of claim 12 wherein the message scheduling module comprises a plurality of message registers, wherein each of the plurality of the message registers function to operate in one of a load mode and a word-shift mode such that each one of the plurality of the message registers is coupled to other of the plurality of the message registers and at least one of the plurality of the message registers is coupled to the at least one multiplexer.

14. The SoC of claim 13 wherein the message scheduling module comprises a plurality of logic functions coupled to at least one of the message register among the plurality of message registers to generate the sequence of message words.

15. The SoC of claim 10 wherein the round computation module comprise at least one multiplexer to select the operating in one of the SHA mode or the SM3 mode.

16. The SoC of claim 15 wherein the round computation module comprises a plurality of state registers, wherein each of the plurality of state registers is coupled to the at least one multiplexer and store a current state value based on one of the SHA mode or the SM3 mode.

17. The SoC of claim 16 wherein the round computation module comprise a plurality of logic functions to process the current state in each of the state registers using the sequence of words and a constant value to generate an updated current state, wherein the constant value is a first constant value in the SM3 mode and the constant value is a second constant value in the SHA mode, wherein the first constant value is different from the second constant value.

18. The SoC of claim 10 wherein the sequence of message words comprise a single message word in the SHA mode and wherein the sequence of message words comprise a pair of message words in the SM3 mode, wherein one message word in the pair of message words is the single message word and other message word in the pair of message words is different from the single message word.

19. A processing system comprising:

a processing core; and

a hardware accelerator communicatively coupled to the processing core, the hardware accelerator comprising:

a plurality of message registers, wherein each of the plurality of the message registers function to operate in one of a load mode or a word-shift mode such that each one of the plurality of the message registers is coupled to other of the plurality of the message registers and at least one of the plurality of the message registers is coupled to the multiplexer;

a plurality of first logic functions coupled to at least one of the message register among the plurality of message registers to generate a sequence of message words;

a plurality of state registers, wherein each of the plurality of state registers store a current state value; and

a plurality of second logic functions to process the current state in each of the state registers using the sequence of words and a constant value to generate an updated current state, wherein the plurality of second logic functions further comprise:

a first shared circuit to perform at least one of a Maj function or a FF function; and

a second shared circuit to perform at least one of a Ch function or a GG function.

20. A system-on-a chip (SoC) comprising:

a memory; and

a processor, communicatively coupled to the memory, comprising:

a processing core; and

a hardware accelerator communicatively coupled to the processing core, the hardware accelerator comprising:

a plurality of message registers, wherein each of the plurality of the message registers function to operate in one of a load mode and a word-shift mode such that each one of the plurality of the message registers is coupled to other of the plurality of the message registers and at least one of the plurality of the message registers is coupled to the multiplexer;

a plurality of first logic functions coupled to at least one of the message register among the plurality of message registers to generate a sequence of message words;

a plurality of state registers, wherein each of the plurality of state registers store a current state value; and

a plurality of second logic functions to process the current state in each of the state registers using the sequence of words and a constant value to generate an updated current state, wherein the plurality of second logic functions further comprise:

a first shared circuit to perform at least one of a Maj function or a FF function; and

a second shared circuit to perform at least one of a Ch function or a GG function.