Granted Patent B2

US 12,288,064 · App. 17/884,739 · Granted Apr 29, 2025

Inventors: Manoj Kumar (Yorktown Heights, NY); Silvia Melitta Mueller (St. Ingbert, DE); Debapriya Chatterjee (Austin, TX); Niels Fricke (Herrenberg, DE); Martijn Diede Berkers (Boeblingen, DE)

Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION

G06F9/30101G06F9/3802H04L9/0643G09C1/00H04L2209/12H04L2209/20

Abstract

Claims (68)

1. A processor, comprising:

an instruction fetch unit that fetches instructions to be executed;

a register file including a plurality of registers for storing source and destination operands; and

an execution unit for executing a message padding instruction among the instructions, wherein the message padding instruction includes an operand field indicating one of the plurality of registers buffering a message block segment of a message block to be padded and a mode field indicating which one of a plurality of different hash functions is to be applied to the message block, wherein the execution unit includes a padding circuit configured, based on execution of the message padding instruction by the execution unit, to perform:

receiving the message block segment from one of the plurality of registers indicated by the operand field of the message padding instruction, wherein the message block spans multiple registers in the register file;

based on which one of the plurality of different hash functions is indicated by the mode field of the message padding instruction, determining whether at least one padding byte is to be inserted within the message block segment;

based on determining that the at least one padding byte is to be inserted within the message block segment, selecting a byte location among multiple byte locations in the message block segment at which to insert the at least one padding byte based on which one of the plurality of different hash function is indicated by the mode field and inserting the at least one padding byte at the selected byte location within the message block segment;

based on determining that the at least one padding byte is not to be inserted within the message block segment, refraining from inserting any padding byte within the message block segment; and

writing the message block segment as processed by the padding circuit back to the register file;

wherein the padding circuit includes at least one enable circuit configured to generate an enable vector to select the byte location and an OR circuit coupled to receive the enable vector and the message block segment and configured to insert, based on the enable vector, the at least one padding byte at the selected byte location in the message block segment.

2. The processor of claim 1 , wherein the plurality of different hash functions includes SHA3, SHAKE, and SHA2 hash functions.

3. The processor of claim 1 , wherein:

the message block includes multiple message block segments; and

the padding circuit is configured to detect, based on an indication in an extension field of the message padding instruction, which of the multiple message block segments the message block segment is.

4. The processor of claim 1 , wherein:

the plurality of different hash functions includes a first hash function and a second hash function; and

the padding circuit is configured to insert both end-of-message (EOM) padding and end-of-block (EOB) padding in the message block segment based on the mode field indicating the first hash function and is configured to insert EOM padding but not EOB padding in the message block segment based on the mode field indicating the second hash function.

5. The processor of claim 1 , wherein: the plurality of hash functions includes a first hash function and a second hash function;

the selecting includes selecting the byte location based on a length parameter stored in the register indicated by the operand mode field of the message padding instruction; and

the padding circuit is configured to insert the at least one padding byte at a first byte location based on the length parameter given the mode field indicating the first hash function and to insert the at least one padding byte at a different second byte location based on the length parameter given the mode field indicating the second hash function.

6. The processor of claim 1 , wherein:

the padding circuit includes a select circuit configured to select a value of the at least one padding byte among multiple different values based on which one of the plurality of different hash functions is indicated by the mode field of the padding instruction.

7. The processor of claim 1 , wherein:

the register file is a first register file;

the plurality of registers is a first plurality of registers;

the processor includes a second register file including a second plurality of registers each having a length less than that of the first plurality of registers;

the execution unit is further configured to assemble multiple chunks of the message block segment in multiple registers among the second plurality of registers and transfer all of the multiple chunks into one of the first plurality of registers to form the message block segment.

8. The processor of claim 7 , wherein the processor is further configured to insert end-of-block (EOB) padding into one of the multiple registers among the second plurality of registers prior to transfer of the multiple chunks to said one of the first plurality of registers.

9. The processor of claim 1 , wherein:

the enable vector has a length in bits corresponding to a length of the message block segment in bytes; and

inserting the at least one padding byte includes inserting the at least one padding byte at the byte location in the message block segment identified by the enable vector.

10. The processor of claim 1 , wherein:

inserting the at least one padding byte includes logically combining an end-of-block (EOB) padding byte with an end-of-message (EOM) padding byte utilizing a Boolean operation to obtain a combined padding byte and inserting the combined padding byte.

11. The processor of claim 1 , wherein:

the execution unit includes a hash circuit that is configured, based on a hash instruction among the instructions, to apply a hash function among the SHA family of hash functions to a padded message block including the message block segment as padded.

12. The processor of claim 1 , wherein:

the message block segment is a portion of a message comprising a plurality of message blocks having an identical length of r bits;

the message block, as padded, includes r bits; and

each of the plurality of registers has a length of less than r bits.

13. A method of data processing in a processor including a register file, said method comprising:

fetching, by an instruction fetch unit of the processor, instructions to be executed by the processor, wherein the instructions include a message padding instruction including an operand field indicating one of the plurality of registers buffering a message block segment of a message block to be padded and a mode field indicating which one of a plurality of different hash functions is to be applied to the message block; and

based on receiving the message padding instruction, an execution unit of the processor executing the message padding instruction, wherein executing the message padding instruction includes:

receiving, from the register file, the message block segment from one of the plurality of registers indicated by the operand field of the message padding instruction, wherein the message block spans multiple registers in the register file;

based on which one of the plurality of different hash functions is indicated by the mode field of the message padding instruction, determining whether at least one padding byte is to be inserted within the message block segment;

based on determining that the at least one padding byte is to be inserted within the message block segment, selecting a byte location among multiple byte locations in the message block segment at which to insert the at least one padding byte based on which one of the plurality of different hash function is indicated by the mode field and inserting the at least one padding byte at the selected byte location within the message block segment, wherein:

the selecting includes generating by an enable circuit an enable vector specifying the byte location; and

the inserting includes merging by an OR circuit, coupled to receive the enable vector and the message block segment, the at least one padding byte and the message block vector;

based on determining that the at least one padding byte is not to be inserted within the message block segment, refraining from inserting any padding byte within the message block segment; and

writing the message block segment as processed by the padding circuit back to the register file.

14. The method of claim 13 , wherein:

the message block includes multiple message block segments; and

the method further comprising detecting, based on an indication in an extension field of the message padding instruction, which of the multiple message block segments the message block segment is.

15. The method of claim 13 , wherein:

the plurality of different hash functions includes a first hash function and a second hash function; and

the executing includes inserting both end-of-message (EOM) padding and end-of-block (EOB) padding in the message block segment based on the mode field indicating the first hash function and is configured to insert EOM padding but not EOB padding in the message block segment based on the mode field indicating the second hash function.

16. The method of claim 13 , wherein: the plurality of hash functions includes a first hash function and a second hash function;

the selecting includes selecting the byte location based on a length parameter stored in the register indicated by the mode field of the message padding instruction; and

the inserting includes inserting the at least one padding byte at a first byte location based on the length parameter given the mode field indicating the first hash function and inserting the at least one padding byte at a different second byte location based on the length parameter given the mode field indicating the second hash function.

17. The method of claim 13 , further comprising:

selecting, by the execution unit, a value of the at least one padding byte among multiple different values based on which one of a plurality of different hash functions is indicated by the mode field of the padding instruction.

18. The method of claim 13 , wherein:

the register file of the processor is a first register file;

the plurality of registers is a first plurality of registers;

the processor includes a second register file including a second plurality of registers each having a length less than that of the first plurality of registers;

the method further comprises assembling multiple chunks of the message block segment in multiple registers among the second plurality of registers and transferring all of the multiple chunks into one of the first plurality of registers to form the message block segment.

19. The method of claim 18 , further comprising inserting end-of-block (EOB) padding into one of the multiple registers among the second plurality of registers prior to transfer of the multiple chunks to said one of the first plurality of registers.

20. The method of claim 13 , further comprising:

based on a hash instruction among the instructions, applying, by hash circuit of the processor, a hash function among the SHA family of hash functions to a padded message block including the message block segment as padded.

Assignments (1)

Continuity (1)

References Cited (89)