Architecture and instruction set for implementing advanced encryption standard (AES)
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
1. A system comprising:
a system memory to store instructions and data; and
a processor comprising:
a plurality of cores;
a level 1 (L1) instruction cache to store instructions;
a level 1 (L1) data cache to store data;
instruction fetch circuitry to fetch the instructions from the L1 instruction cache;
decode circuitry to decode a Single Instruction Multiple Data (SIMD) instruction specifying that only a single encryption round of the Advanced Encryption Standard (AES) is to be performed, wherein the SIMD instruction has an encrypt/decrypt parameter that is dedicated to specification of whether either one of the single encryption round or a single decryption round of the AES is to be performed;
a Read Only Memory (ROM) to store micro-operations for the SIMD instruction;
a first 128-bit source register to store first input data;
a second 128-bit source register to store second input data; and
an execution unit including AES execution circuitry, wherein, in response to execution of the SIMD instruction, the AES execution circuitry is to execute the micro-operations to perform a plurality of operations to perform only the single encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform, and a shift rows transform, and is to store a result to a 128-bit destination storage location.
2. The system of claim 1 , wherein the byte substitution transform comprises a substitution of one or more bytes using data retrieved from a substitution table.
3. The system of claim 1 , further comprising:
a scheduler to schedule operations to be executed by the processor.
4. The system of claim 1 , further comprising:
circuitry to write the result of the SIMD instruction to the 128-bit destination storage location.
5. The system of claim 1 , further comprising:
a storage device coupled to the processor to store instructions and data.
6. The system of claim 1 , wherein the system memory comprises a dynamic random access memory (DRAM).
7. The system of claim 1 , further comprising:
an input/output (I/O) controller to couple the processor to one or more I/O devices.
8. The system of claim 1 , further comprising:
a Serial Advanced Technology Attachment (SATA) controller to couple the processor to one or more SATA storage devices.
9. The system of claim 1 , wherein the SIMD instruction has:
a parameter to specify a key size; and
a parameter to indicate if the single encryption round is a last round.
10. The system of claim 1 , wherein the processor further comprises a retirement unit.
11. The system of claim 1 , wherein the processor further comprises key generation logic to generate the round key.
12. The system of claim 1 , wherein the SIMD instruction has a parameter dedicated to specification of whether the single encryption round is a final round.
13. The system of claim 1 , wherein the processor further comprises a retirement unit, wherein the processor further comprises key generation logic to generate the round key, and wherein the SIMD instruction has a parameter dedicated to specification of whether the single encryption round is a final round.
14. A system comprising:
a system memory to store instructions and data; and
a processor comprising:
a level 1 (L1) instruction cache to store instructions;
a level 1 (L1) data cache to store data;
an instruction decoder to decode a Single Instruction Multiple Data (SIMD) instruction specifying that only a single encryption round of the Advanced Encryption Standard (AES) is to be performed, wherein the SIMD instruction has an encrypt/decrypt parameter that is dedicated to specification of whether either one of the single encryption round or a single decryption round of the AES is to be performed;
a Read Only Memory (ROM) to store micro-operations for the SIMD instruction;
a scheduler to schedule operations for execution;
a first 128-bit source register to store first input data;
a second 128-bit source register to store second input data; and
an execution unit including AES execution circuitry, wherein, in response to execution of the SIMD instruction, the execution unit is to execute the micro-operations to perform a plurality of operations to perform only the single encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform, and a shift rows transform, and is to store a result of the SIMD instruction to a 128-bit destination storage location.
15. The system of claim 14 , wherein the byte substitution transform comprises a substitution of one or more bytes using data retrieved from a substitution table, wherein a result of the byte substitution transform comprises an array of substituted data, and wherein the shift rows transform is to shift data in each row of a first array by a specified amount to result in a second array.
16. The system of claim 15 , further comprising a storage device coupled to the processor to store instructions and data.
17. The system of claim 16 , wherein the system memory comprises a dynamic random access memory (DRAM).
18. The system of claim 17 , further comprising an input/output (I/O) controller to couple the processor to one or more I/O devices.
19. The system of claim 18 , further comprising a Serial Advanced Technology Attachment (SATA) controller to couple the processor to one or more SATA storage devices, and wherein the processor further comprises a retirement unit, and wherein the SIMD instruction has a parameter to specify a key size, and a parameter to indicate if the single encryption round is a last round.
20. A system comprising:
a system memory to store instructions and data; a processor comprising:
a level 1 (L1) instruction cache to store instructions;
a level 1 (L1) data cache to store data;
an instruction decoder to decode a Single Instruction Multiple Data (SIMD) instruction specifying that only a single encryption round of the Advanced Encryption Standard (AES) is to be performed, wherein the SIMD instruction can be used for both encryption and decryption and has a parameter dedicated to specification of whether the encryption or the decryption is to be performed;
a Read Only Memory (ROM) to store micro-operations for the SIMD instruction;
a scheduler to schedule operations for execution;
a first 128-bit source register to store first input data;
a second 128-bit source register to store second input data;
an execution unit including AES execution circuitry, wherein, in response to execution of the SIMD instruction, the execution unit is to execute the micro-operations to perform a plurality of operations to perform only the single encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform that is to substitute bytes using data retrieved from a substitution table, and a shift rows transform that is to shift data in each row of a first array by a specified amount to produce a second array, and is to store a result of the SIMD instruction to a 128-bit destination storage location; and
a retirement unit; and
a Serial Advanced Technology Attachment (SATA) controller to couple the processor to one or more SATA storage devices.
21. The system of claim 20 , wherein the parameter is an encrypt/decrypt parameter to specify whether the single encryption round or a single decryption round of the AES is to be performed.
22. The system of claim 20 , wherein the SIMD instruction has a parameter to specify a key size, and a parameter to indicate if the single encryption round is a last round, wherein the system memory comprises a dynamic random access memory (DRAM), and further comprising a storage device coupled to the processor to store instructions and data.
23. A system comprising:
a system memory to store instructions and data; and
a processor comprising:
a level 1 (L1) instruction cache to store instructions; a level 1 (L1) data cache to store data;
instruction fetch circuitry to fetch the instructions from the L1 instruction cache;
decode circuitry to decode a Single Instruction Multiple Data (SIMD) instruction specifying that only a single encryption round of the Advanced Encryption Standard (AES) is to be performed, wherein the SIMD instruction has an encrypt/decrypt parameter that is dedicated to specification of whether either one of the single encryption round or a single decryption round of the AES is to be performed;
a first 128-bit source register to store first input data;
a second 128-bit source register to store second input data;
execution circuitry, wherein, in response to execution of the SIMD instruction, the execution circuitry is to perform a plurality of operations to perform only the single encryption round, including an exclusive OR (XOR) of the first input data and the second input data, a byte substitution transform, and a shift rows transform, and is to store a result to a 128-bit destination storage location; and
a retirement unit.