Hardware accelerator for cryptographic hash operations

1. A processor comprising:

a hardware accelerator for performing a cryptographic hash algorithm, the hardware accelerator comprising:

a plurality of message registers to store a plurality of message words of a message to be processed using the cryptographic hash algorithm;

a plurality of digest registers to store digest words A-H, wherein each digest word has a size of W bits, wherein each digest word comprises a plurality of portions that each have a size of N bits, wherein the plurality of digest registers includes a first digest register, a second digest register, and a fifth digest register; and

circuitry to:

perform a plurality of rounds of the cryptographic hash algorithm using the plurality of digest registers and the plurality of message registers, wherein each round comprises a plurality of Y cycles, wherein the plurality of rounds is divided into a first set of rounds and a second set of rounds, wherein the first set and the second set are selected from a set of even-numbered rounds and a set of odd-numbered rounds,

cause the first digest register to store digest word A during each round in the first set and to store digest word B during each round in the second set;

cause the second digest register to store digest word B during each round in the first set and to store digest word A during each round in the second set; and

cause the fifth digest register to store digest word C during each of the plurality of rounds.

2. The processor of claim 1 , wherein the circuitry is further to:

in each cycle of each round in the first set:

use W bits from the first digest register for a first function, use N bits from the second digest register for a second function, and use N bits from the fifth digest register for the second function;

in each cycle of each round in the second set:

use W bits from the second digest register for the first function, use N bits from the first digest register for the second function, and use N bits from the fifth digest register for the second function.

3. The processor of claim 1 , wherein portion size N is equal to word size W divided by number of cycles Y.

4. The processor of claim 1 , wherein:

the hardware accelerator comprises a first hardware switch and a second hardware switch,

wherein the first hardware switch is to cause the first digest register to store digest word A during each round in the first set and to store digest word B during each round in the second set, and

wherein the second hardware switch is to cause the second digest register to store digest word B during each round in the first set and to store digest word A during each round in the second set.

5. The processor of claim 1 , wherein:

the cryptographic hash algorithm is a Secure Hash Algorithm 2 (SHA-2);

the first function is a Σ 0 function of the SHA-2 algorithm; and

the second function is a Maj function of the SHA-2 algorithm.

6. The processor of claim 1 , wherein the plurality of digest registers further includes a third digest register and a fourth digest register, and wherein the hardware accelerator is further to:

in each cycle of each round in the first set, use W bits from the third digest register for a third function, and use N bits from the fourth digest register for a fourth function; and

in each cycle of each round in the second set, use W bits from the fourth digest register for the third function, and use N bits from the third digest register for the fourth function.

7. The processor of claim 6 , wherein the circuitry is further to:

in each round in the first set, store digest word E in the third digest register and store digest word F in the fourth digest register; and

in each round in the second set, store digest word E in the fourth digest register and store digest word F in the third digest register.

8. The processor of claim 6 , wherein:

the third function is a Σ 1 function of the cryptographic hash algorithm; and

the fourth function is a Ch function of the cryptographic hash algorithm.

9. A non-transitory machine-readable medium having stored thereon instructions that upon execution cause a processor to perform a method comprising:

receiving a message to be processed using a cryptographic hash algorithm;

initializing a plurality of digest registers to store digest words A-H, wherein each digest word comprises W bits, wherein each digest word comprises a plurality of portions that each have a size of N bits, wherein the plurality of digest registers includes a first digest register, a second digest register, and a fifth digest register;

performing a plurality of rounds of the cryptographic hash algorithm using the plurality of digest registers, wherein the plurality of rounds is divided into a first set and a second set, the first set and the second selected from a set of even-numbered rounds and a set of odd-numbered rounds;

in each round in the first set:

storing digest word A in the first digest register;

storing digest word B in the second digest register; and

storing digest word C in the fifth digest register;

in each round in the second set:

storing digest word A in the second digest register;

storing digest word B in the first digest register; and

storing digest word C in the fifth digest register.

10. The non-transitory machine-readable medium of claim 9 , wherein the method further comprises:

in each cycle of each round in the first set:

using W bits from the first digest register for a first function;

using N bits from the second digest register for a second function; and

using N bits from the fifth digest register for the second function;

in each cycle of each round in the second set:

using W bits from the second digest register for the first function;

using N bits from the first digest register for the second function; and

using N bits from the fifth digest register for the second function.

11. The non-transitory machine-readable medium of claim 10 , wherein the plurality of digest registers further includes a third digest register and a fourth digest register, and wherein the method further comprises:

in each cycle of each round in the first set, using W bits from the third digest register for a third function, and using N bits from the fourth digest register for a fourth function;

in each cycle of each round in the second set, using W bits from the fourth digest register for the third function, and using N bits from the third digest register for the fourth function.

12. The non-transitory machine-readable medium of claim 11 , wherein the method further comprises:

in each round in the first set:

storing digest word E in the third digest register; and

storing digest word F in the fourth digest register;

in each round in the second set:

storing digest word E in the fourth digest register; and

storing digest word F in the third digest register.

13. The non-transitory machine-readable medium of claim 9 , wherein each round comprises a plurality of Y cycles, wherein portion size N is equal to word size W divided by number of cycles Y, wherein word size W is selected from 32 bits and 64 bits, and wherein portion size N is selected from 2 bits and 4 bits.

14. The non-transitory machine-readable medium of claim 9 , wherein:

the cryptographic hash algorithm is a Secure Hash Algorithm 2 (SHA-2);

the first function is a Σ 0 function of the cryptographic hash algorithm;

the second function is a Maj function of the cryptographic hash algorithm;

the third function is a Σ 1 function of the cryptographic hash algorithm; and

the fourth function is a Ch function of the cryptographic hash algorithm.

15. A system comprising:

a hardware processor comprising an accelerator for performing a cryptographic hash algorithm, the accelerator comprising:

a plurality of digest registers to store digest words A-H; and

circuitry to:

perform a plurality of rounds of the cryptographic hash algorithm using the plurality of digest registers, wherein each round comprises a plurality of C cycles, wherein the plurality of rounds is divided into a first set and a second set selected from a set of even-numbered rounds and a set of odd-numbered rounds;

cause a first digest register to store digest word A during each round in the first set and to store digest word B during each round in the second set;

cause a second digest register to store digest word B during each round in the first set and to store digest word A during each round in the second set;

cause a fifth digest register to store digest word C during each of the plurality of rounds; and

an external memory coupled to the hardware processor.

16. The system of claim 15 , wherein each digest word comprises W bits, wherein each digest word comprises a plurality of portions that each have a size of N bits, and wherein the circuitry is further to:

in each cycle of each round of the first set:

use W bits from the first digest register for a first function of the cryptographic hash algorithm, use N bits from the second digest register for a second function of the cryptographic hash algorithm, and use N bits from the fifth digest register for the second function;

in each cycle of each round of the second set:

use W bits from the second digest register for the first function, use N bits from the first digest register for the second function, and use N bits from the fifth digest register for the second function.

17. The system of claim 15 , wherein the circuitry is further to:

in each cycle of each round in the first set, use W bits from a third digest register for a third function of the cryptographic hash algorithm, and use N bits from a fourth digest register for a fourth function of the cryptographic hash algorithm;

in each cycle of each round in the second set, use W bits from the fourth digest register for the third function, and use N bits from the third digest register for the fourth function.

18. The system of claim 17 , wherein:

the third function is a Σ 1 function of the cryptographic hash algorithm; and

the fourth function is a Ch function of the cryptographic hash algorithm.

19. The system of claim 15 , wherein:

the first function is a Σ 0 function of the cryptographic hash algorithm; and

the second function is a Maj function of the cryptographic hash algorithm.

20. The system of claim 15 , wherein the cryptographic hash algorithm is SHA-2 algorithm.