Method and system of programmable resistive devices with read capability using a low supply voltage
A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to at least one selector and at least one read selector. The read selector includes at least one read source line (SLR) and/or one read enable (ENR) coupled to a second and/or a third supply voltage lines, respectively. The read selector includes at least one MOS device built by core logic device. The PRE in the at least one PRD cells can be configured to be readable by applying voltages to the first, second, and/or the third voltage supply lines to thereby sense the PRE resistance to a logic state. The programmable resistive element can have at least one element in an OTP, MTP, floating gate device, anti-fuse, or emerging memory such as PCRAM, RRAM, or MRAM, etc.
1. A Programmable Resistive Device (PRD) memory, comprising:
a plurality of PRD memory cells, at least one of the PRD memory cells including at least:
a Programmable Resistive Element (PRE) having one end coupled to a first supply voltage line and the other end coupled to an element selector and a read selector;
the read selector having an read source input (SLR) and/or a read enable input (ENR) coupled to a second supply voltage line and/or a third supply voltage line, respectively, and
wherein the PRE is configured to be readable by applying voltages to the first, second, and/or the third supply voltage lines to conduct current flowing through the PRE to thereby sense the PRE resistance into a logic state.
2. A PRD memory as recited in claim 1 , wherein the read selector has at least one MOS device built from core logic devices.
3. A PRD memory as recited in claim 1 , wherein the element selector has at least one MOS device built by I/O devices.
4. A PRD memory as recited in claim 1 , wherein the element selector and/or the read selector includes at least one Schottky diode.
5. A PRD memory as recited in claim 1 , wherein the element selector has a source input (SL) and/or an enable signal input (EN) coupled to a fourth and/or fifth supply voltage lines, respectively; wherein the PRE is configured to be programmable by applying voltages to the first, fourth and/or fifth supply voltage lines and thereby change the PRE into another logic state.
6. A PRD memory as recited in claim 5 , wherein the read source line (SLR) and/or read enable (ENR) is let floating during programming the PRE into a different logic state.
7. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) is a One-Time Programmable (OTP) element that can be programmed only once.
8. A PRD memory as recited in claim 7 , wherein the OTP Element is constructed from at least one of a polysilicon, silicide, silicided polysilicon, CMOS metal gate, metal interconnect, polymetal, local interconnect, metal alloy, or thermally isolated active area.
9. A PRD memory as recited in claim 7 , wherein the OTP Element is constructed from at least one conductive contact or via.
10. A PRD memory as recited in claim 7 , wherein the OTP Element is an anti-fuse device fabricated by at least one contact or via with dielectric in between, or an anti-fuse comprising of a CMOS gate and a CMOS body with gate oxide in between.
11. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) is constructed from at least one floating-gate device.
12. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) includes at least one thin film and wherein the PRD memory is a Phase-Change Memory (PCRAM), Resistive Memory (RRAM), Conductive Bridging Memory (CBRAM), or Magnetic Memory (MRAM).
13. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) comprises a film of phase change material including at least one of Germanium (Ge), Antimony (Sb), and Tellurium (Te).
14. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) comprises at least one metal-oxide film between metal or metal alloy electrodes.
15. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) comprises at least one solid-state electrolyte film between metal or metal oxide electrodes.
16. A PRD memory as recited in claim 1 , wherein the Programmable Resistive Element (PRE) comprises at least one Magnetic Tunnel Junction (MTJ).
17. An electronic system, comprising:
a processor; and
a Programmable Resistive Device (PRD) memory operatively connected to the processor, the PRD memory including a plurality of PRD memory cells, at least one of the PRD memory cells comprising:
a Programmable Resistive Element (PRE) having one end operatively coupled to a first supply voltage line and the other end coupled to at least a first selector and a second selector, the second selector having an read source input (SLR) and/or a read enable input (ENR) coupled to a second supply voltage line and/or a third supply voltage line, respectively,
wherein the PRE is configured to be readable by applying voltages to first, second, and/or third supply voltage lines to conduct current flowing through the PRE to thereby sense the PRE resistance into a logic state.
18. An electronic system as recited in claim 17 , wherein the second selector has at least one MOS device built from core logic devices.
19. An electronic system as recited in claim 17 , wherein the read source line (SLR) and/or read enable (ENR) is let floating during programming the PRE into a different logic state.
20. A method for operating a Programmable Resistive Device (PRD) memory, the method comprises:
providing a plurality of PRD cells, at least one of the PRD cells includes at least (i) a Programmable Resistive Element (PRE) coupled to a first supply voltage line, (ii) a first selector including a source line (SL) and/or an enable signal line (EN), (iii) a second selector including a read source line (SLR) and/or a read enable line (ENR) coupled to a second and/or a third supply voltage line, respectively, and
reading a logic state from the at least one of the PRD cells by applying voltages to the first, second, and/or third voltage lines and by turning on the second selector.
21. A method for operating a PRD memory as recited in claim 20 , wherein the second selector includes at least one MOS device built from core logic device.
22. A method for operating a PRD memory as recited in claim 20 , wherein the read source line (SLR) and/or read enable (ENR) is let floating during programming the PRE into a different logic state.