Memory device

1. A memory device, comprising:

a plurality of selection lines extending in a first direction and spaced apart from each other in a second direction, the selection lines comprising first to third selection lines sequentially arranged in the second direction;

a plurality of vertical pillars each coupled to a corresponding one of the selection lines;

a sub-interconnection extending over adjacent ones of the selection lines; and

a bit line connected to the sub-interconnection and extending in the second direction,

wherein the vertical pillars are disposed to form a matrix-shaped arrangement and include first to third vertical pillars constituting first to third columns, respectively, which are sequentially arranged in the second direction.

2. The memory device of claim 1 , wherein the sub-interconnection comprises:

a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line; and

a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line.

3. The memory device of claim 2 , further comprising third sub-interconnections connected to the second vertical pillar.

4. The memory device of claim 3 , wherein the bit line comprises first to third bit lines sequentially arranged in the first direction, and

the first to third sub-interconnections are each connected to a respective one of the bit lines.

5. The memory device of claim 4 , wherein the sub-interconnections are connected to the vertical pillars, respectively, via lower contacts provided on the vertical pillars, and

the bit lines are connected to the sub-interconnections, respectively, via upper contacts provided on the sub-interconnections.

6. The memory device of claim 2 , wherein the bit line comprises first to third bit lines sequentially arranged in the first direction,

wherein the first and second sub-interconnections are connected to the first and third vertical pillars, respectively, via first lower contacts provided on the first and third vertical pillars,

wherein two of the bit lines are connected to the first and second sub-interconnections, respectively, via first upper contacts provided on the first and second sub-interconnections,

wherein the remaining one of the bit lines is connected to the second vertical pillar via a second lower contact and a second upper contact, which are sequentially stacked on the second vertical pillar coupled with each of the selection lines to be in contact with each other.

7. A memory device, comprising:

first and second vertical pillars coupled with a selection line extending in a first direction and sequentially arranged in a second direction that intersects the first direction;

a first sub-interconnection connected to the first vertical pillar via a first lower contact on the first vertical pillar;

a second sub-interconnection connected to the second vertical pillar via a second lower contact on the second vertical pillar;

a first bit line connected to the first sub-interconnection via a first upper contact and extending in the second direction, the first upper contact being offset from the first vertical pillar in the first direction; and

a second bit line connected to the second sub-interconnection via a second upper contact and extending in the second direction, the second upper contact being offset from the second vertical pillar in the direction opposite to the first direction.

8. The memory device of claim 7 , further comprising:

a third vertical pillar arranged between the first and second vertical pillars; and

a third bit line provided between the first bit line and the second bit line and connected to the third vertical pillar via a third lower contact and a third upper contact, which overlap with the third vertical pillar.

9. A memory device, comprising:

first and second selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction;

vertical pillars, each coupled with a corresponding one of the first and second selection lines;

a sub-interconnection connecting one of the vertical pillars coupled with the first selection line to one of the vertical pillars coupled with the second selection line; and

a bit line extending in the second direction and connected to the sub-interconnection, and

wherein at least one of the vertical pillars coupled with one of the first and second selection lines is not connected with any vertical pillar coupled with the other of the first and second selection lines.