IP Library Granted Patent US 9,696,937
Granted Patent B2
US 9,696,937 · App. 14/940,248 · Granted Jul 4, 2017

Memory system data management

Inventor: Ramin Ghodsi (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F3/0647G06F3/0604G06F3/0619G06F3/0679G06F12/0246G06F12/0802G06F12/0284G06F12/0804G06F2212/1016G06F2212/1032G06F2212/2022G06F2212/60G06F2212/7201G06F2212/7203
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Quick Facts
Patent No.
US 9,696,937
App. No.
14/940,248
Granted
Jul 4, 2017
Kind
B2
Abstract

The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

Claims (30)

1. A method for managing data in a memory system, comprising:

generating a notification with a memory device that indicates the memory device is ready to receive data from a buffer;

sending the notification from the memory device to the buffer; and

writing a number of portions of data to the memory device in the memory system in response to receiving the notification, wherein the buffer allocates data from the buffer to the memory device in response to receiving the notification and wherein the number of portions of data are sent from the buffer to the memory device in response to receiving the notification.

2. The method of claim 1 , wherein sending the notification from the memory device to the buffer includes sending a next available address in the memory device.

3. The method of claim 2 , wherein the method includes determining the next available address in the memory device based on a location in the memory device that is ready to receive data and on a wear strategy implemented on the memory device.

4. The method of claim 1 , wherein the method includes sending data from a next available data address in the buffer.

5. The method of claim 1 , wherein the method includes recording, in a transaction table, a logical address and a physical address of each of the number of portions of data written to the memory device.

6. The method of claim 5 , wherein the method includes storing the transaction table in the buffer.

7. The method of claim 5 , wherein the method includes storing the transaction table in the memory device.

8. The method of claim 1 , wherein the method includes performing an error correction (ECC) operation on the data prior to writing the data to the buffer.

9. A method for managing data in a memory system, comprising:

writing data from a host to a buffer in the memory system; and

writing a number of portions of the data to a number of memory devices in the memory system in response to the buffer receiving a number of notifications sent from the number of memory devices that indicate that the memory devices are ready to receive and write data and wherein the number of portions of data are sent from the buffer to the number of memory devices in response to receiving the number of notifications.

10. The method of claim 9 , wherein writing the number of portions of the data in the buffer to the number of memory devices includes writing the number of portions of data to the number of memory devices in an order in which the number of notifications from the number of memory devices are received by the buffer.

11. The method of claim 9 , wherein the method includes performing wear operations on at least one of the number of memory devices.

12. The method of claim 9 , wherein the method includes performing an error correction (ECC) operation on the data prior to writing the data to the buffer.

13. The method of claim 9 , wherein writing data from the host to the buffer includes writing data to the buffer in increments that are the size of a NAND page.

14. The method of claim 9 , wherein writing the number of portions of the data in the buffer to the number of memory devices includes writing the number of portions of data in NAND page increments.

15. An apparatus, comprising:

a number of memory devices; and

a buffer coupled to the number of memory devices and configured to:

receive data from a host and write the data in the buffer;

allocate at least a portion of the data from the buffer to one of the number of memory devices in response to receiving a notification from the one of the number of memory devices that the one of the number of memory devices is ready to receive data; and

send the portion of the data from the buffer to the one of the number of memory devices in response to the portion of the data being allocated to the one of the number of memory devices.

16. The apparatus of claim 15 , wherein the one of the number of memory devices is configured to send another notification to the buffer that includes another next available address to write data when the one of the number of memory devices has completed all operations scheduled to be performed by the one of the number of memory devices.

17. The apparatus of claim 15 , wherein the buffer includes a number of volatile memory cells.

18. The apparatus of claim 15 , wherein the number of memory devices comprise a number of groups of non-volatile memory cells.

19. The apparatus of claim 15 , wherein the buffer is configured to store a logical address and a physical address of the portion of data sent to the one of the number of memory devices in a transaction table.

20. The apparatus of claim 19 , wherein a copy of the transaction table is periodically stored in the number of memory devices and the copy of the transaction table is sent to the buffer upon power up the apparatus.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2015
From: GHODSI, RAMIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 037030/0505 →
Continuity (2)
Continuation 14068574 · Oct 31, 2013
Related Publication 20160070508A1 · Mar 10, 2016