IP Library Granted Patent US 9,922,678
Granted Patent B2
US 9,922,678 · App. 14/947,833 · Granted Mar 20, 2018

Error correction for storage devices

Inventors: Gregory Burd (San Jose, CA); Nedeljko Varnica (San Jose, CA); Heng Tang (San Jose, CA)
Assignee: Marvell World Trade Ltd.
G11B20/1833G06F11/08G06F11/1076G11B20/1217G11B2020/1222G11B2020/1238
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Quick Facts
Patent No.
US 9,922,678
App. No.
14/947,833
Granted
Mar 20, 2018
Kind
B2
Abstract

Systems and techniques include a method including: receiving a data request for first data stored at a storage device; reading second data from discrete units of storage of the storage device, the second data comprising the first data read from two or more of the discrete units of storage, error correction code redundancies read from the two or more of the discrete units of storage, and parity data read from at least one of the discrete units of storage; detecting, based on the error correction code redundancies, an error in a first portion of the first data stored in one of the two or more of the discrete units of storage; and recovering the first portion of the first data using the parity data and a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.

Claims (27)

1. A method comprising:

receiving, at a storage controller, a data request for first data stored at a storage device;

reading, in response to the data request, second data from discrete units of storage of the storage device, the second data comprising i) the first data read from two or more of the discrete units of storage, ii) error correction code redundancies read from the two or more of the discrete units of storage, and iii) parity data read from at least one of the discrete units of storage;

detecting, based on the error correction code redundancies read from the two or more of the discrete units of storage, an error in a first portion of the first data, wherein the first portion of the first data with the error is stored in one of the two or more of the discrete units of storage; and

recovering the first portion of the first data with the error using i) the parity data and ii) a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.

2. The method of claim 1 , wherein each of the error correction code redundancies is associated with a wordline, wherein each wordline comprises a single page for storing data.

3. The method of claim 1 , wherein each of the error correction code redundancies is associated with a wordline, wherein each wordline comprises a plurality of pages for storing data.

4. The method of claim 1 , wherein error correction code redundancies are done on a wordline level.

5. The method of claim 4 , wherein the storage device is a single level cell (SLC) solid state memory device.

6. The method of claim 4 , wherein the storage device is a multi level cell (MLC) solid state memory device.

7. The method of claim 1 , wherein the at least one of the discrete units of storage from which the parity data is read comprises at least one dedicated parity device.

8. The method of claim 1 , wherein the storage device is a solid state memory device, and each of the discrete units of storage is a page in the solid state memory device.

9. The method of claim 8 , wherein the reading comprises reading pages in accordance with an interleaving across physical memory blocks of the solid state memory device.

10. A storage system comprising:

discrete units of storage in a storage device; and

a controller, coupled to the discrete units of storage in the storage device, to

read, in response to a data request for first data, second data from the discrete units of storage in the storage device, the second data comprising i) the first data read from two or more of the discrete units of storage, ii) error correction code redundancies read from the two or more of the discrete units of storage, and iii) parity data read from at least one of the discrete units of storage,

detect, based on the error correction code redundancies, an error in a first portion of the first data, wherein the first portion of the first data with the error is stored in one of the two or more of the discrete units of storage, and

recover the first portion of the first data with the error using i) the parity data and ii) a second portion of the first data read from one or more remaining ones of the two or more of the discrete units of storage.

11. The storage system of claim 10 , wherein each of the error correction code redundancies is associated with a wordline, wherein each wordline comprises a single page for storing data.

12. The storage system of claim 10 , wherein each of the error correction code redundancies is associated with a wordline, wherein each wordline comprises a plurality of pages for storing data.

13. The storage system of claim 10 , wherein error correction code redundancies are done on a wordline level.

14. The storage system of claim 13 , wherein the storage device is a single level cell (SLC) solid state memory device.

15. The storage system of claim 13 , wherein the storage device is a multi level cell (MLC) solid state memory device.

16. The storage system of claim 10 , wherein the at least one of the discrete units of storage from which the parity data is read comprises at least one dedicated parity device.

17. The storage system of claim 10 , wherein the storage device is a solid state memory device, and each of the discrete units of storage is a page in the solid state memory device.

18. The storage system of claim 17 , wherein the controller reads pages from the solid state memory device in accordance with an interleaving across physical memory blocks of the solid state memory device.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
Continuity (9)
Continuation 14642526 · Mar 9, 2015
Continuation 14466881 · Aug 22, 2014
Continuation In Part 14260237 · Apr 23, 2014
Continuation 13844302 · Mar 15, 2013
Continuation 12881881 · Sep 14, 2010
Provisional Application 61876360 · Sep 11, 2013
Provisional Application 61254577 · Oct 23, 2009
Provisional Application 61242662 · Sep 15, 2009
Related Publication 20160078898A1 · Mar 17, 2016