Methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
1. A method of forming a semiconductor construction, comprising:
forming vertically-stacked memory cells along a vertically-extending channel material;
forming an insulative material over the channel material;
forming a first semiconductor material over the insulative material;
forming metal-containing material over the first semiconductor material;
forming a first opening to extend through the metal-containing material and the first semiconductor material to the insulative material;
forming a gate dielectric along sidewalls and a bottom of the first opening;
forming a second opening through the gate dielectric at the bottom of the first opening and through the insulative material; and
forming second semiconductor material within the first and second openings; a portion of the second semiconductor material within the first opening being spaced from the first semiconductor material and the metal-containing material by at least the gate dielectric and being a transistor channel region.
2. The method of claim 1 further comprising forming a semiconductor material liner along sidewalls of the first opening prior to forming the gate dielectric.
3. The method of claim 2 wherein the semiconductor material liner comprises silicon.
4. The method of claim 1 further comprising forming an electrically conductive liner along sidewalls of the first opening prior to forming the gate dielectric.
5. The method of claim 1 further comprising:
forming spacer material along the gate dielectric within the first opening prior to forming the second opening; and
utilizing the spacer material as a mask during formation of the second opening.
6. The method of claim 5 wherein the spacer material comprises semiconductor material and is incorporated into the transistor channel region.
7. The method of claim 5 further comprising removing the spacer material prior to forming the second semiconductor material within the first and second openings.