Method and structure of three-dimensional chip stacking

1. A method comprising:

placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer;

bonding the first composite wafer to a second wafer, wherein the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding, wherein after the bonding, the first plurality of device dies is located between the first carrier and the second wafer;

de-bonding the first carrier from the first plurality of device dies;

encapsulating the first plurality of device dies in an encapsulating material; and

forming an interconnect structure over the first plurality of device dies and the encapsulating material.

2. The method of claim 1 , wherein during the bonding, empty spaces exist between the first plurality of device dies, and the method further comprises forming a plurality of through-vias on the second wafer before bonding the first composite wafer to the second wafer, and in the bonding the first composite wafer to the second wafer, the plurality of through-vias extends into the empty spaces.

3. The method of claim 2 , wherein when the bonding is performed, the plurality of through-vias is spaced apart from the first composite wafer.

4. The method of claim 1 further comprising:

forming a plurality of through-vias on the first composite wafer, wherein the encapsulating the first plurality of device dies is performed on the first composite wafer, and in the bonding, the encapsulating material contacts, and is not bonded to, the second plurality of device dies.

5. The method of claim 1 further comprising forming the second wafer comprising:

placing a second plurality of device dies over a second carrier, with the second plurality of device dies and the second carrier in combination forming the second wafer that is a second composite wafer, and the encapsulating material encircles both the first plurality of device dies and the second plurality of device dies.

6. The method of claim 1 , wherein the hybrid bonding comprises:

bonding first bond pads of the first plurality of device dies to second bond pads of the second plurality of device dies; and

bonding first surface dielectric layers of the first plurality of device dies to second surface dielectric layers of the second plurality of device dies, and the method further comprises forming air gaps surrounding the first bond pads.

7. The method of claim 1 , wherein each of the first plurality of device dies comprises:

a semiconductor substrate; and

additional through-vias penetrating through the semiconductor substrate, wherein the encapsulating the first plurality of device dies comprises a planarization step to thin the first plurality of device dies and to expose the additional through-vias.

8. A method comprising:

placing a first plurality of device dies over a carrier, wherein before being placed on the carrier, the first plurality of device dies is discrete dies separated from each other;

forming a plurality of through-vias on a second plurality of device dies of a wafer;

aligning the first plurality of device dies on the carrier to the second plurality of device dies;

bonding the first plurality of device dies to the second plurality of device dies through hybrid bonding, wherein the plurality of through-vias extends into spaces between the first plurality of device dies;

de-bonding the carrier from the first plurality of device dies;

encapsulating the first plurality of device dies in an encapsulating material;

performing a planarization to level top surfaces of the first plurality of device dies, the encapsulating material, and the plurality of through-vias; and

forming an interconnect structure over the first plurality of device dies and the encapsulating material.

9. The method of claim 8 , wherein the hybrid bonding comprises:

pre-bonding the first plurality of device dies to the second plurality of device dies; and

annealing the first plurality of device dies and the second plurality of device dies to form the hybrid bonding.

10. The method of claim 9 , wherein the annealing is performed on both the first plurality of device dies and the carrier.

11. The method of claim 9 , wherein the annealing is performed with top surfaces of the first plurality of device dies exposed.

12. The method of claim 8 , wherein after the planarization, the plurality of through-vias is exposed.

13. The method of claim 8 , wherein the aligning is performed by aligning alignment marks to the plurality of through-vias, wherein the alignment marks are attached to the carrier.

14. The method of claim 13 , wherein each of the alignment marks overlaps one of the plurality of through-vias.

15. A method comprising:

bonding a first wafer to a second wafer, wherein a first plurality of device dies in the first wafer are bonded to a second plurality of device dies in the second wafer through hybrid bonding, and portions of the first wafer are inserted into spaces between portions of the second wafer;

encapsulating the first plurality of device dies in an encapsulating material, wherein the encapsulating material further encapsulates a plurality of conductive posts of the second plurality of device dies;

performing a Chemical Mechanical Polish (CMP) to reveal the first plurality of device dies and the plurality of conductive posts; and

forming redistribution lines over the first plurality of device dies, wherein the redistribution lines are electrically connected to the plurality of conductive posts.

16. The method of claim 15 , wherein the hybrid bonding comprises:

pre-bonding the first plurality of device dies to the second plurality of device dies;

separating the first wafer into pieces; and

annealing the first plurality of device dies and the second plurality of device dies to form hybrid bonds, wherein the annealing is performed before the first wafer is separated into individual pieces.

17. The method of claim 15 , wherein the hybrid bonding comprises:

pre-bonding the first plurality of device dies to the second plurality of device dies;

separating the first wafer into pieces; and

annealing the first plurality of device dies and the second plurality of device dies to form the hybrid bonding, wherein the annealing is performed with top surfaces of the first plurality of device dies revealed.

18. The method of claim 15 further comprising aligning the first wafer to the second wafer by aligning alignment marks in the first wafer to the plurality of conductive posts of the second wafer.

19. The method of claim 18 , wherein each of the alignment marks overlaps one of the plurality of conductive posts.

20. The method of claim 15 further comprising attaching the first plurality of device dies to a carrier to form the first wafer.