Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus
A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
1. An imaging device comprising:
a first wafer including a pixel array having a plurality of photoelectric conversion portions and a first wiring layer;
a second wafer including a second wiring layer;
a third wafer including a third wiring layer;
a first connection layer disposed between the first wafer and the second wafer;
a second connection layer disposed between the second wafer and third wafer;
a first via extending from the first wafer to the second wafer and penetrating the first connection layer;
a second via disposed in the second wafer;
a third via extending from the second wafer to the third wafer and penetrating the second connection layer; and
a connecting portion disposed in the second wafer,
wherein,
the first via includes a first point in the second wafer connected to a first region of the connecting portion,
the second via includes second and third points, the second point connected to a second region of the connecting portion and the third point connected to a wiring in the second wiring layer, and
the third via includes a fourth point in the second wafer and a fifth point in the third wafer, the fourth point connected to a third region of the connecting portion and the fifth point connected to a wiring in the third wiring layer.
2. The imaging device of claim 1 , wherein the first via is electrically connected to a wiring in the first wiring layer.
3. The imaging device of claim 1 , wherein the first wafer includes a first substrate and a first insulating layer and the first wiring layer is within the first insulating layer.
4. The imaging device of claim 3 , wherein the second wafer includes a second substrate and a second insulating layer and the second wiring layer is within the second insulating layer.
5. The imaging device of claim 4 , further including a third insulating layer disposed between the first connection layer and the second substrate.
6. The imaging device of claim 4 , wherein the third wafer includes a third substrate and a third insulating layer and the third wiring layer is within the third insulating layer.
7. The imaging device of claim 1 , further including a fourth via extending from the first wafer to the second wafer and penetrating the second connection layer, wherein the fourth via is electrically connected to a wiring in the first wiring layer and a second wiring in the second wiring layer.
8. The imaging device of claim 7 , wherein the first via is electrically connected to a second wiring in the first wiring layer.
9. The imaging device of claim 1 , wherein a logic circuit is formed in the third wafer.
10. An electronic apparatus comprising:
an imaging device;
an optical system which introduces incident light to a photodiode of the imaging device; and
a signal processing circuit which processes an output signal of the imaging device, the imaging device including:
a first wafer including a pixel array having a plurality of photodiodes and a first wiring layer;
a second wafer including a second wiring layer;
a third wafer including a third wiring layer;
a first connection layer disposed between the first wafer and the second wafer;
a second connection layer disposed between the second wafer and third wafer;
a first via extending from the first wafer to the second wafer and penetrating the first connection layer;
a second via disposed in the second wafer;
a third via extending from the second wafer to the third wafer and penetrating the second connection layer; and
a connecting portion disposed in the second wafer,
wherein,
the first via includes a first point in the second wafer connected to a first region of the connecting portion,
the second via includes second and third points, the second point connected to a second region of the connecting portion and the third point connected to a wiring in the second wiring layer, and
the third via includes a fourth point in the second wafer and a fifth point in the third wafer, the fourth point connected to a third region of the connecting portion and the fifth point connected to a wiring in the third wiring layer.
11. The electronic apparatus of claim 10 , wherein the first via is electrically connected to a wiring in the first wiring layer.
12. The electronic apparatus of claim 10 , wherein the first wafer includes a first substrate and a first insulating layer and the first wiring layer is within the first insulating layer.
13. The electronic apparatus of claim 12 , wherein the second wafer includes a second substrate and a second insulating layer and the second wiring layer is within the second insulating layer.
14. The electronic apparatus of claim 13 , further including a third insulating layer disposed between the first connection layer and the second substrate.
15. The electronic apparatus of claim 13 , wherein the third wafer includes a third substrate and a third insulating layer and the third wiring layer is within the third insulating layer.
16. The electronic apparatus of claim 10 , further including a fourth via extending from the first wafer to the second wafer and penetrating the second connection layer, wherein the fourth via is electrically connected to a first wiring in the first wiring layer and a second wiring in the second wiring layer.
17. The electronic apparatus of claim 16 , wherein the first via is electrically connected to a second wiring in the first wiring layer.
18. The electronic apparatus of claim 10 , wherein a logic circuit is formed in the third wafer.