Antenna assembly for wafer level packaging
Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (RF) signal; a printed circuit board (PCB) attached to a front side of the package substrate, where the PCB includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity.
1. A radio frequency (RF) semiconductor device comprising:
a package substrate comprising:
an embedded die configured to process a radio frequency (RF) signal, and
embedded interconnects between an active side of the embedded die and a front side of the package substrate, wherein the embedded interconnects have contact areas exposed at the front side of the package substrate;
a printed circuit board (PCB) having a first side and a second side that opposes the first side, wherein the PCB includes a cavity that extends from the first side to the second side of the PCB,
wherein the first side of the PCB is attached to the front side of the package substrate by a plurality of solder connections that are attached to a first subset of the contact areas of the embedded interconnects exposed at the front side of the package substrate, and
wherein the PCB is configured to:
provide ground to the embedded die through a first solder connection of the plurality of solder connections, and
provide a power supply voltage to the embedded die through a second solder connection of the plurality of solder connections; and
an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity between the first side and the second side of the PCB.
2. The RF semiconductor device of claim 1 , wherein the antenna enabling element comprises a connector for an antenna.
3. The RF semiconductor device of claim 1 , wherein the antenna enabling element comprises a structure that includes an antenna, the structure comprising one of a group including a ball grid array (BGA) package, a land grid array (LGA) package, and a dedicated antenna structure.
4. The RF semiconductor device of claim 1 , wherein the antenna enabling element comprises an antenna, the antenna comprising one of a group including a patch antenna, a microstrip antenna, and an aperture antenna.
5. The RF semiconductor device of claim 1 , wherein
the active side of the embedded die is proximal to the front side of the package substrate, a backside of the embedded die is proximal to and surrounded by a package body of the package substrate, and
the embedded interconnects are formed in a layout for a fan out wafer level package (FOWLP).
6. The RF semiconductor device of claim 1 , wherein the antenna enabling element extends through at least a portion of the PCB.
7. The RF semiconductor device of claim 1 , wherein the package substrate further comprises a plurality of buildup layers over the embedded die that form the embedded interconnects, and the plurality of buildup layers comprises a top conductive layer having portions exposed on the front side of the package substrate to form the contact areas of the embedded interconnects.
8. The RF semiconductor device of claim 7 , wherein the antenna enabling element is attached to the front side of the package substrate by another plurality of solder connections that are attached to a second subset of contact areas of the embedded interconnects exposed at the front side of the package substrate.
9. The RF semiconductor device of claim 7 , wherein a shielding layer is formed from the top conductive layer on the front side of the package substrate, the shielding layer located between the antenna enabling element and the embedded die.
10. The RF semiconductor device of claim 1 , wherein a frequency of the RF signal is measured in millimeters.
11. The RF semiconductor device of claim 1 , wherein the embedded die is positioned within the package substrate to underlie the cavity.
12. The RF semiconductor device of claim 1 , wherein the cavity is positioned on an edge of the PCB.
13. The RF semiconductor device of claim 1 , wherein the cavity is positioned in a corner of the PCB.
14. The RF semiconductor device of claim 1 , wherein the front side of the package substrate comprises one or more openings in a dielectric material to form one or more external contact areas.
15. The RF semiconductor device of claim 14 , wherein the front side of the package substrate further comprises one or more portions of an exposed conductive layer over the dielectric material to form one or more additional external contact areas.
16. The RF semiconductor device of claim 1 , wherein
the antenna enabling element is coupled to the embedded die by a signal path, and
the signal path comprises one or more from a group including solder connections on the front side of the package substrate and embedded interconnects in the package substrate.
17. The RF semiconductor device of claim 16 , wherein the signal path between the antenna enabling element and the embedded die is less than 100 microns.
18. The RF semiconductor device of claim 1 , wherein the embedded die comprises a transmitter and the RF signal is conveyed from the first side of the PCB to the second side of the PCB through the cavity.
19. The RF semiconductor device of claim 1 , wherein the embedded die comprises a receiver and the RF signal is conveyed from the second side of the PCB to the first side of the PCB through the cavity.
20. A packaged semiconductor device comprising:
an integrated circuit die embedded in a package body, wherein the integrated circuit die has an active side exposed in a top surface of the package body, the integrated circuit die is configured to process a radio frequency (RF) signal;
a plurality of buildup layers over and contacting the active side of the integrated circuit die and the top surface of the package body, wherein the plurality of buildup layers form a plurality of embedded interconnects to the integrated circuit die, wherein the plurality of embedded interconnects have contact areas exposed at a top buildup layer;
an antenna enabling element attached to a first subset of contact areas; and
a printed circuit board (PCB) having a first side attached a second subset of contact areas by a plurality of solder connections,
wherein the PCB is configured to:
provide ground to the integrated circuit die through a first solder connection of the plurality of solder connections, and
provide a power supply voltage to the integrated circuit die through a second solder connection of the plurality of solder connections,
wherein at least a portion of the PCB is located laterally to the antenna enabling element, and the antenna enabling element is configured to convey the RF signal between the first side of the PCB and a second side of the PCB that opposes the first side.
21. The packaged semiconductor device of claim 20 , wherein the antenna enabling element comprises a structure that includes an antenna, the structure comprising one of a group including a ball grid array (BGA) package, a land grid array (LGA) package, and a dedicated antenna structure.
22. The packaged semiconductor device of claim 20 , wherein the antenna enabling element comprises an antenna, the antenna comprising one of a group including a patch antenna, a microstrip antenna, and an aperture antenna.