Granted Patent B2

US 9,640,723 · App. 14/966,124 · Granted May 2, 2017

Abstract

Claims (25)

1. A method of fabricating a semiconductor device, comprising:

forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core;

forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface;

removing a portion of the insulating material layer to define an active region of nanowires;

forming a conductive material layer over at least a portion of the insulating material layer and the plurality of nanowires in the active region; and

forming an electrical contact over the substantially planar top surface of the insulating material layer,

wherein:

the electrical contact is electrically connected to the conductive material layer; and

the conductive material layer comprises a p-electrode which contacts the second conductivity type semiconductor shell of the nanowires in the active region.

2. The method of claim 1 , further comprising forming a dielectric layer over active region after removing a portion of the insulating material layer to define an active region.

3. The method of claim 2 , wherein the dielectric layer comprises a spin on glass.

4. The method of claim 1 , further comprising forming a conductive n-contact which contacts an n-type buffer layer located on the support.

5. The method of claim 4 , wherein n-type cores of the plurality of nanowires contact the n-type buffer layer.

6. The method of claim 1 , wherein the conductive material layer comprises indium tin oxide.

7. The method of claim 1 , wherein the conductive material layer is located on at least a portion of the substantially planar top surface of insulating material layer and the electrical contact is located on the conductive material layer in a region over the substantially planar top surface of the insulating material layer.

8. A semiconductor device, comprising:

a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core;

an insulating material layer that forms a boundary around the plurality of nanowires to define an active region of nanowires, the insulating material layer having a substantially planar top surface;

a conductive material layer comprising a p-electrode located on at least a portion of the substantially planar top surface of insulating material layer and contacting the second conductivity type semiconductor shell of the plurality of nanowires in the active region; and

an electrical contact located on the conductive material layer in a region over the substantially planar top surface of the insulating material layer.

9. The semiconductor device of claim 8 , further comprising a dielectric layer located over active region.

10. The semiconductor device of claim 9 , wherein the dielectric layer comprises a spin on glass.

11. The semiconductor device of claim 8 , further comprising a conductive n-contact which contacts an n-type buffer layer located on the support.

12. The semiconductor device of claim 11 , wherein n-type cores of the plurality of nanowires contact the n-type buffer layer.

13. The semiconductor device of claim 8 , wherein the conductive material layer comprises indium tin oxide.

Assignments (9)