Method and apparatus for determining a timing adjustment of output to a host memory controller

1. A device implemented in a first memory module coupled to a bus connected to a host memory controller and a second memory module, wherein the second memory module includes memory chips, the first memory module comprising:

memory chips to store data, wherein the first and second memory modules are separately and independently connected to the bus; and

a first memory module controller to:

determine a difference of at least one hardware component between the first memory module and the second memory module that results in a timing difference of output of data between the first memory module and the second memory module;

determine a timing adjustment based on the timing difference of the at least one hardware component to cause output from the first memory module to the host memory controller to match a timing of output of data at the second memory module to the host memory controller to account for the timing difference between the first memory module and the second memory module, wherein the timing adjustment is to:

accelerate the timing in response to the first memory module having at least one hardware component effecting timing of the output of data that is not included in the second memory module; and

add a delay to the timing in response to the second memory module having at least one hardware component effecting the timing of the output of data at the second memory module that is not included in the first memory module; and

adjust a timing of an output of data to the host memory controller based on the timing adjustment to match a timing of output of data at the second memory module, wherein the timing of the output of data to the host memory controller on the bus from both the first and the second memory modules matches before reaching the host memory controller.

2. The device of claim 1 , wherein the timing adjustment comprises both accelerate the timing and add the delay, wherein the timing adjustment comprises a net of the accelerate and the add the delay.

3. The device of claim 1 , wherein the at least one hardware component comprises a data buffer in the first memory module, wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module does not include a data buffer such as included in the first memory module.

4. The device of claim 1 , wherein the at least one hardware component comprises a register in the second memory module, wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module includes the register that is not included in the first memory module.

5. The device of claim 4 , wherein the register in the second memory module is on a command, address and control busses.

6. The device of claim 1 , wherein the output of data having the timing adjusted comprises output from a data buffer of the first memory module.

7. The device of claim 1 , wherein the first and second memory modules comprise different types of dual in-line memory modules (DIMMs).

8. The device of claim 7 , wherein the second memory module comprises one of an unbufferred DIMM (UDIMM), registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

9. The device of claim 8 , wherein the timing adjustment comprises accelerating the timing of the output of data when the first memory module includes a data buffer and the second memory module comprises a UDIMM.

10. The device of claim 8 , wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module comprises the RDIMM and the first memory module does not include a register and accelerating the timing of the output of data when the first memory module includes a data buffer on the output of data.

11. The device of claim 8 , wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module comprises the LRDIMM and the first memory module does not include a data buffer.

12. An apparatus comprising:

a host memory controller;

a bus;

a first memory module and a second memory module coupled to the host memory controller over the bus, wherein the first and the second memory modules each include memory chips to store data, wherein the second memory module includes a second memory module controller, and wherein the first and second memory modules are separately and independently connected to the bus;

a first memory module controller implemented in the first memory module to:

determine a difference of at least one hardware component between the first memory module and the second memory module that results in a timing difference of output of data between the first memory module and the second memory module;

determine a timing adjustment based on the timing difference of the at least one hardware component to cause output from the first memory module to the host memory controller to match a timing of output of data at the second memory module to the host memory controller to account for the timing difference between the first memory module and the second memory module, wherein the determined timing adjustment is to:

accelerate the timing in response to the first memory module having at least one hardware component effecting timing of the output of data that is not included in the second memory module; and

add a delay to the timing in response to the second memory module having at least one hardware component effecting the timing of the output of data at the second memory module that is not included in the first memory module; and

adjust a timing of an output of data to the host memory controller based on the timing adjustment to match a timing of output of data at the second memory module, wherein the timing of the output of data to the host memory controller on the bus from both the first and the second memory modules matches before reaching the host memory controller.

13. The apparatus of claim 12 , wherein the timing adjustment comprises both accelerate the timing and add the delay, wherein the determined timing adjustment comprises a net of the accelerate and the add the delay.

14. The apparatus of claim 12 , wherein the at least one hardware component comprises a data buffer in the first memory module, wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module does not include a data buffer such as included in the first memory module.

15. The apparatus of claim 12 , wherein the at least one hardware component comprises a register in the second memory module, wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module includes the register that is not included in the first memory module.

16. The apparatus of claim 12 , wherein the first and second memory modules comprise different types of dual in-line memory modules (DIMMs).

17. A method for determining a timing adjustment for a first memory module coupled to a bus connected to a host memory controller and a second memory module, wherein the first and second memory module each include memory chips and controllers, comprising:

determining a difference of at least one hardware component between the first memory module and the second memory module that results in a timing difference of output of data between the first memory module and the second memory module, and wherein the first and second memory modules are separately and independently connected to the bus;

determining a timing adjustment based on the timing difference of the at least one hardware component to cause output from the first memory module to the host memory controller to match a timing of output of data at the second memory module to the host memory controller to account for the timing difference between the first memory module and the second memory module, wherein the determined timing adjustment is to:

accelerate the timing in response to the first memory module having at least one hardware component effecting timing of the output of data that is not included in the second memory module; and

add a delay to the timing in response to the second memory module having at least one hardware component effecting the timing of the output of data at the second memory module that is not included in the first memory module; and

adjusting a timing of an output of data to the host memory controller based on the timing adjustment to match a timing of output of data at the second memory module, wherein the timing of the output of data to the host memory controller on the bus from both the first and the second memory modules matches before reaching the host memory controller.

18. The method of claim 17 , wherein the timing adjustment comprises both accelerating the timing and adding the delay, wherein the timing adjustment comprises a net of the accelerating and the adding the delay.

19. The method of claim 17 , wherein the at least one hardware component comprises a data buffer in the first memory module, wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module does not include a data buffer such as included in the first memory module.

20. The method of claim 17 , wherein the at least one hardware component comprises a register in the second memory module, wherein the timing adjustment comprises delaying the timing of the output of data when the second memory module includes the register that is not included in the first memory module.

21. The method of claim 17 , wherein the output of data having the timing adjusted comprises output of data from a data buffer of the first memory module.

22. The method of claim 17 , wherein the first and second memory modules comprise different types of dual in-line memory modules (DIMMs).