IP Library › Granted Patent US 12,468,445
Granted Patent B2
US 12,468,445 · App. 18/408,558 · Granted Nov 11, 2025

Coordinated in-module RAS features for synchronous DDR compatible memory

Inventors: Mu-Tien Chang (Santa Clara, CA); Dimin Niu (Sunnyvale, CA); Hongzhong Zheng (Los Gatos, CA); Sun Young Lim (Gyeonggi-Do, KR); Indong Kim (Kyunggi-Do, KR); Jangseok Choi (San Jose, CA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/061G06F3/0619G06F3/0625G06F3/0652G06F3/0653G06F3/0673G06F11/106G11C29/52G11C5/04G11C11/40611G11C2029/0409G11C2029/0411
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,468,445
App. No.
18/408,558
Granted
Nov 11, 2025
Kind
B2
Abstract

A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

Claims (40)

1 . A method comprising:

receiving, by a controller, a command using an interface, the interface comprising a connection based on an in-line memory module terminal configuration to provide status information of a memory array; and

controlling, by the controller, the interface to provide the status information using the interface based on a result of a correction operation of the memory array.

2 . The method of claim 1 , further comprising:

controlling, by the controller, a refresh operation of the memory array, and

controlling, by the controller, the interface to provide the status information based on the refresh operation.

3 . The method of claim 1 , further comprising:

controlling, by the controller, a refresh operation of the memory array, and

controlling, by the controller, the interface to provide the status information based on a status of the refresh operation.

4 . The method of claim 3 , wherein the status information indicates a status of a rank identification for a refresh operation.

5 . The method of claim 3 , wherein the status information indicates a status of a bank identification for a refresh operation.

6 . The method of claim 1 , further comprising:

controlling, by the controller, a scrubbing operation of the memory array, and

controlling, by the controller, the interface to provide the status information based on the scrubbing operation.

7 . The method of claim 1 , wherein the memory array comprises non-volatile memory, the method further comprising:

controlling, by the controller, a wear-leveling operation of the memory array, and

controlling, by the controller, the interface to provide the status information based on the wear-leveling operation.

8 . A method, comprising:

controlling, by a controller, a wear-leveling operation of a memory array, the memory array comprising an array of memory cells, the array of memory cells comprising volatile memory and non-volatile memory, the memory array configured as an in-line memory module; and

providing, by the controller, using an interface comprising a connection based on an in-line memory module terminal configuration, status information based on the wear-leveling operation.

9 . The method of claim 8 , further comprising providing, by the controller, using the interface, scheduling information based on the wear-leveling operation.

10 . The method of claim 8 , further comprising:

controlling, by the controller, a refresh operation of the memory array, and providing, by the controller, using the interface, the status information based on the refresh operation.

11 . The method of claim 8 , further comprising:

controlling, by the controller, a correction operation of the memory array, and providing, by the controller, the status information based on the correction operation and that indicates a result of the correction operation.

12 . The method of claim 11 , further comprising:

controlling, by the controller, a scrubbing operation of the memory array, and providing, by the controller, using the interface, the status information based on the scrubbing operation.

13 . The method of claim 8 , wherein:

the in-line memory module terminal configuration comprises a terminal to provide a first type of information; and

the connection uses the terminal to provide a second type of information comprising the status information of the memory array.

14 . A method, comprising:

controlling, by a controller, using an interface, an operation of a memory array, wherein the memory array is configured as a an in-line memory module, and the in-line memory module comprises a connection based on a an in-line memory module terminal configuration;

receiving, by the controller, using the interface, a command; and

providing, by the controller, using the interface, status information based on the command relating to an operation controlled by the controller.

15 . The method of claim 14 , wherein the operation comprises at least one of a refresh operation of a memory array, a correction operation of the memory array, a memory scrubbing operation of the memory array, or a wear-leveling operation of the memory array.

16 . The method of claim 14 , wherein the controller controls a refresh operation of the memory array, and the method further comprises controlling, by the controller, the interface based on the refresh operation of the memory array to provide the status information based on the refresh operation.

17 . The method of claim 14 , wherein the controller controls a correction operation of the memory array, and the method further comprises controlling, by the controller, the interface to provide the status information indicating a result of the correction operation.

18 . The method of claim 17 , further comprising controlling, by the controller, the interface to provide the status information that indicates an action based on the result of the correction operation.

19 . The method of claim 14 , wherein the controller controls a memory scrubbing operation of the memory array, and the method further comprises controlling, by the controller, the interface to provide the status information based on the memory scrubbing operation.

20 . The method of claim 14 , wherein the memory array comprises a two or more non-volatile memory cells, the controller controls a wear-leveling operation of the memory array, and the method further comprises controlling, by the controller, the interface to provide the status information based on the wear-leveling operation.

Continuity (9)
Continuation 17713228 · Apr 4, 2022
Continuation 16819032 · Mar 13, 2020
Continuation 15213386 · Jul 18, 2016
Provisional Application 62347569 · Jun 8, 2016
Provisional Application 62303352 · Mar 3, 2016
Provisional Application 62303349 · Mar 3, 2016
Provisional Application 62303347 · Mar 3, 2016
Provisional Application 62303343 · Mar 3, 2016
Related Publication 20240143173A1 · May 2, 2024
References Cited (109)
US 5737258A · Choi et al. · 1998 [cited by applicant]
US 5907867A · Shinbo et al. · 1999 [cited by applicant]
US 6154821A · Barth et al. · 2000 [cited by applicant]
US 6445624B1 · Janzen et al. · 2002 [cited by applicant]
US 6735037B1 · Tanaka et al. · 2004 [cited by applicant]
US 7062618B2 · Tsunoda et al. · 2006 [cited by applicant]
US 7269709B2 · Kelly · 2007 [cited by applicant]
US 7379316B2 · Rajan · 2008 [cited by applicant]
US 7386768B2 · Vogt et al. · 2008 [cited by applicant]
US 7394720B2 · Kim et al. · 2008 [cited by applicant]
US 7421558B2 · Choi et al. · 2008 [cited by applicant]
US 7620783B2 · Wolford et al. · 2009 [cited by applicant]
US 7716411B2 · Panabaker et al. · 2010 [cited by applicant]
US 7917688B2 · Tanaka et al. · 2011 [cited by applicant]
US 8064250B2 · Abdulla · 2011 [cited by applicant]
US 8130574B2 · Ngo et al. · 2012 [cited by applicant]
US 8261136B2 · D'Abreu et al. · 2012 [cited by applicant]
US 8359521B2 · Kim et al. · 2013 [cited by applicant]
US 8588017B2 · Park et al. · 2013 [cited by applicant]
US 8737148B2 · Byom et al. · 2014 [cited by applicant]
US 8745321B2 · Rajan et al. · 2014 [cited by applicant]
US 8924639B2 · Ahn et al. · 2014 [cited by applicant]
US 8938581B2 · Cho et al. · 2015 [cited by applicant]
US 9032162B1 · Chang et al. · 2015 [cited by applicant]
US 9104547B2 · Baltar · 2015 [cited by applicant]
US 9214199B2 · Brandl et al. · 2015 [cited by applicant]
US 9405608B2 · Okubo et al. · 2016 [cited by applicant]
US 9460791B1 · Shallal et al. · 2016 [cited by applicant]
US 9569144B2 · Uematsu et al. · 2017 [cited by applicant]
US 9830086B2 · Niu et al. · 2017 [cited by applicant]
US 10152370B2 · Nale · 2018 [cited by applicant]
US 10268257B2 · Nomura · 2019 [cited by applicant]
US 10592114B2 · Chang · 2020 [cited by examiner]
US 10902890B2 · Bains · 2021 [cited by applicant]
US 20010003198A1 · Wu · 2001 [cited by applicant]
US 20040243753A1 · Horowitz et al. · 2004 [cited by applicant]
US 20050066137A1 · Jeddeloh et al. · 2005 [cited by applicant]
US 20050188137A1 · Fujiki · 2005 [cited by applicant]
US 20060090054A1 · Choi et al. · 2006 [cited by applicant]
US 20070162720A1 · Branda et al. · 2007 [cited by applicant]
US 20080082750A1 · Okin et al. · 2008 [cited by applicant]
US 20090037666A1 · Rahman et al. · 2009 [cited by applicant]
US 20090168524A1 · Golov · 2009 [cited by examiner]
US 20100005214A1 · Trombley et al. · 2010 [cited by applicant]
US 20100110748A1 · Best · 2010 [cited by applicant]
US 20100332943A1 · D'Abreu et al. · 2010 [cited by applicant]
US 20110276775A1 · Schuetz · 2011 [cited by applicant]
US 20120173809A1 · Ko · 2012 [cited by applicant]
US 20120331356A1 · Vogt et al. · 2012 [cited by applicant]
US 20130097369A1 · Talagala et al. · 2013 [cited by applicant]
US 20140181364A1 · Berke et al. · 2014 [cited by applicant]
US 20140192583A1 · Rajan et al. · 2014 [cited by applicant]
US 20140237157A1 · Takefman et al. · 2014 [cited by applicant]
US 20140359391A1 · Pawlowski · 2014 [cited by applicant]
US 20150186042A1 · Lee · 2015 [cited by applicant]
US 20150268959A1 · Krishna et al. · 2015 [cited by applicant]
US 20150309742A1 · Amidi et al. · 2015 [cited by applicant]
US 20160041861A1 · Chang · 2016 [cited by examiner]
US 20160085585A1 · Chen et al. · 2016 [cited by applicant]
CN 1311509A · 2001 [cited by applicant]
CN 1503974A · 2004 [cited by applicant]
CN 101042929A · 2007 [cited by applicant]
CN 101751226A · 2010 [cited by applicant]
CN 103765392A · 2014 [cited by applicant]
CN 104050099A · 2014 [cited by applicant]
CN 104409097A · 2015 [cited by applicant]
CN 204332379U · 2015 [cited by applicant]
EP 2458505B1 · 2012 [cited by applicant]
EP 2706461A1 · 2014 [cited by applicant]
JP H08306195A · 1996 [cited by applicant]
JP 2001010865A · 2001 [cited by applicant]
JP 2001014842A · 2001 [cited by applicant]
JP 2003091463A · 2003 [cited by applicant]
JP 2005537543A · 2005 [cited by applicant]
JP 2008171163A · 2008 [cited by applicant]
JP 2009526323A · 2009 [cited by applicant]
JP 2009540431A · 2009 [cited by applicant]
JP 2010134201A · 2010 [cited by applicant]
JP 2010153018A · 2010 [cited by applicant]
JP 2011530734A · 2011 [cited by applicant]
JP 2012089137A · 2012 [cited by applicant]
JP 2012146360A · 2012 [cited by applicant]
JP 2013525924A · 2013 [cited by applicant]
JP 2014157391A · 2014 [cited by applicant]
JP 2014194795A · 2014 [cited by applicant]
JP 2015064758A · 2015 [cited by applicant]
KR 100660892B1 · 2006 [cited by applicant]
KR 20120079682A · 2012 [cited by applicant]
KR 20130141693A · 2013 [cited by applicant]
KR 20150120359A · 2015 [cited by applicant]
KR 20160016896A · 2016 [cited by applicant]
KR 101832552B1 · 2018 [cited by applicant]
TW 1246081B · 2005 [cited by applicant]
TW 201015338A · 2010 [cited by applicant]
TW 1711928B · 2020 [cited by applicant]
WO 2014143056A1 · 2014 [cited by applicant]
WO 2014155593A1 · 2014 [cited by applicant]
WO 2015089054A1 · 2015 [cited by applicant]
Corrected Notice of Allowability for U.S. Appl. No. 17/713,228, mailed Apr. 30, 2024. [cited by applicant]
Corrected Notice of Allowability for U.S. Appl. No. 17/713,228, mailed Jan. 26, 2023. [cited by applicant]
Final Office Action for U.S. Appl. No. 15/213,386, mailed Jan. 11, 2019. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 15/213,386, mailed Oct. 23, 2019. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 16/819,032, mailed Nov. 26, 2021. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/713,228, mailed Jan. 12, 2023. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/713,228, mailed Sep. 13, 2023. [cited by applicant]
Office Action for U.S. Appl. No. 15/213,386, mailed May 17, 2019. [cited by applicant]
Office Action for U.S. Appl. No. 15/213,386, mailed Sep. 21, 2018. [cited by applicant]
Office Action for U.S. Appl. No. 16/819,032, mailed Jul. 6, 2021. [cited by applicant]
Office Action for U.S. Appl. No. 17/713,228, mailed May 1, 2023. [cited by applicant]