Method of manufacturing a package substrate

1. A method for manufacturing a package substrate, comprising:

providing a first copper layer comprising a first face and a second face opposite to the first face, and etching the first copper layer from the first face to form a plurality of protrusions;

laminating a dielectric layer on the protrusions of the first copper layer, the dielectric layer comprising a first side and a second side opposite to the first side;

forming a double copper layers structure on the second side of the dielectric layer and opposite to the first copper layer,

polishing the second face of the first cooper layer to change a height of each of the protrusions to form a first circuit layer comprising a plurality of spaced first circuit patterns embedded into the dielectric layer; and

etching the double copper layers structure to form a plurality of spaced second circuit patterns, the second circuit patterns located outsides the dielectric layer and collectively forming a second circuit layer;

wherein each of the first circuit patterns has an extension direction from the first side toward the second side of the dielectric layer, and has widths thereof gradually decreasing along the extension direction.

2. The method of claim 1 , wherein the double copper layers structure comprises a second copper layer and a third copper layer, the second copper layer is a crystal seed layer formed by chemical plating on the dielectric layer, an electrically conductive pole is formed in the second copper layer by a process of plating through hole, and the third copper layer is formed on the second copper layer by electroplating.

3. The method of claim 2 , wherein the second copper layer is half etched and forms a contact hole by lasing drilling before forming the electrically conductive pole, and the electrically conductive pole is formed by electroplating the contact hole.

4. The method of claim 2 , wherein the electrically conductive pole electrically couples the first copper layer to the second copper layer.

5. The method of claim 1 , further comprising:

forming two solder resist films on outer faces of the first circuit layer and the second circuit layer, respectively;

exposing portions of the first circuit layer and the second circuit layer out of the two solder resist films; and

coating the portions of the first circuit layer and the second circuit layer exposed out of the two solder resist films with organic solderability preservatives.

6. The method of claim 5 , after forming the two solder resist films, further comprising:

exposing, developing treating and etching portions of the solder resist film corresponding to some of the first circuit patterns of the first circuit layer, to forms a plurality of solder resist openings.

7. The method of claim 5 , further comprising:

packaging a circuit module formed by the first circuit layer, the dielectric layer, the electrically conductive pole and the second circuit layer, a method for packaging the circuit module comprising:

providing a chip electrically coupled to the first circuit layer via a plurality of solder balls correspondingly and electrically coupled to the first circuit patterns; and

forming a moulding compound layer covering the solder resist layer on the first circuit layer and surrounding the chip on the first circuit layer.

8. The method of claim 1 , before providing the first copper layer, further comprising:

providing a substrate comprising a base, a copper layer on the base and a nickel layer on the copper layer;

wherein the first copper layer is formed on the nickel layer, and the substrate is removed after forming the double copper layers structure.

9. The method of claim 1 , wherein each of the first circuit patterns has a section of trapezoid.