Method and structure for III-V nanowire tunnel FETs
A heterojunction tunnel field effect transistor (TFET) has a channel region that includes a first portion of a nanowire, a source region and a drain region that respectively include a second portion and a third portion of a nanowire, and a gate that surrounds the channel region, where the first portion of the nanowire comprises an intrinsic, epitaxial III-V semiconductor. The TFET can be made by selectively etching the epitaxial underlayer to define a tethered (suspended) nanowire that forms a channel region of the device. Source and drain regions can be formed from regrown p-type and n-type epitaxial layers.
1. A method of making a tunnel field effect transistor (TFET), comprising:
forming a III-V semiconductor layer directly on a SiGe layer of a semiconductor substrate;
selectively etching the SiGe layer with respect to the III-V semiconductor layer to form a suspended nanowire;
forming a gate structure encapsulating the suspended nanowire; and
forming a source region and a drain region adjacent to respective first and second ends of the nanowire.
2. The method of claim 1 , wherein the III-V semiconductor layer is an epitaxial layer.
3. The method of claim 1 , wherein the III-V semiconductor layer is an intrinsically doped layer.
4. The method of claim 1 , wherein forming the source region comprises epitaxially growing p-type semiconductor material, and forming the drain region comprises epitaxially growing n-type semiconductor material.
5. The method of claim 1 , wherein the source and drain regions each comprise a top surface that is substantially co-planar with a top surface of the nanowire.
6. The method of claim 1 , further comprising defining a channel region by forming a protective mask comprising dielectric spacers and an interlayer dielectric prior to selectively etching the SiGe layer.
7. The method of claim 1 , wherein the III-V semiconductor layer comprises a material selected from the group consisting of GaAs, GaP, GaN, GaAlAs, InGaAs, InAlAs, InP and InAs.
8. The method of claim 1 , wherein the semiconductor substrate comprises a SiGe-on-insulator substrate.