Structure and method for fully depleted silicon on insulator structure for threshold voltage modification
A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.
1. A fully depleted silicon on insulator (FDSOI) device comprising:
a buried oxide layer on a semiconductor substrate;
an alumina charge trapping layer formed directly in the buried oxide layer;
a backgate well in the semiconductor substrate under the charge trapping layer; and
a device structure including a gate structure, source and drain regions disposed over the buried oxide layer,
wherein a threshold voltage of the device is partially established by a charge trapped in the charge trapping layer.
2. The device as recited in claim 1 , further comprising a plurality of regions in the semiconductor substrate, wherein each region has a set of FDSOI devices configured as recited in claim 1 , and wherein a first set of FDSOI devices in a first region of the semiconductor substrate have a first type of and amount of charge and a second set of FDSOI devices in a second region of the substrate have a second type of and amount of charge.
3. The device as recited in claim 2 , wherein the first type of charge is a negative charge and the second type of charge is a positive charge.
4. The device as recited in claim 1 , further comprising a plurality of regions in the semiconductor substrate, wherein each region has a set of FDSOI devices configured as recited in claim 1 , and wherein a first set of FDSOI devices in a first region of the semiconductor substrate have a first type of charge trapped in respective charge trapping layers and an n-type dopant in respective backgate well areas and a second set of FDSOI devices in a second region of the semiconductor substrate have the first type of charge trapped in respective charge trapping layers and a p-type dopant in respective backgate well areas, wherein a threshold voltage of a respective device is dependent on the charge trapped in the charge trapping layer and the dopant in the backgate well area.
5. The device as recited in claim 1 , further comprising a shallow trench isolation area which extends through the buried oxide layer below the level of the charge trapping layer.
6. The device as recited in claim 1 , wherein an amount of charge trapped in the charge trapping layer is according to a measured value of an electrical characteristic.
7. A fully depleted silicon on insulator (FDSOI) device comprising:
a buried oxide layer on a semiconductor substrate;
a charge trapping layer formed directly in the buried oxide layer, wherein the charge trapping layer includes a different material than the buried oxide layer;
a backgate well in the semiconductor substrate under the charge trapping layer; and
a device structure including a gate structure, source and drain regions disposed over the buried oxide layer,
wherein a threshold voltage of the device is partially established by a charge trapped in the charge trapping layer, and
wherein the charge trapping layer in the buried oxide layer is electrically isolated from an adjacent charge trapping layer in the buried oxide layer.
8. The device as recited in claim 7 , wherein the charge trapping layer in the buried oxide layer is electrically isolated from the adjacent charge trapping layer by an oxide material containing no charge trapping layer.
9. The device as recited in claim 7 , wherein the charge trapping layer is an implant-damaged layer in the buried oxide layer.
10. The device as recited in claim 7 , wherein the charge trapping layer is a layer selected from the group of silicon nodules, silicon nitride, and alumina.
11. The device as recited in claim 7 , further comprising a plurality of regions in the semiconductor substrate, wherein each region has a set of FDSOI devices configured as recited in claim 1 , and wherein a first set of FDSOI devices in a first region of the semiconductor substrate have a first type of and amount of charge and a second set of FDSOI devices in a second region of the substrate have a second type of and amount of charge.
12. The device as recited in claim 11 , wherein the first type of charge is a negative charge and the second type of charge is a positive charge.
13. The device as recited in claim 7 , further comprising a plurality of regions in the semiconductor substrate, wherein each region has a set of FDSOI devices configured as recited in claim 1 , and wherein a first set of FDSOI devices in a first region of the semiconductor substrate have a first type of charge trapped in respective charge trapping layers and an n-type dopant in respective backgate well areas and a second set of FDSOI devices in a second region of the semiconductor substrate have the first type of charge trapped in respective charge trapping layers and a p-type dopant in respective backgate well areas, wherein a threshold voltage of a respective device is dependent on the charge trapped in the charge trapping layer and the dopant in the backgate well area.
14. The device as recited in claim 7 , further comprising a shallow trench isolation area which extends through the buried oxide layer below the level of the charge trapping layer.
15. The device as recited in claim 7 , wherein an amount of charge trapped in the charge trapping layer is according to a measured value of an electrical characteristic.