IP Library › Granted Patent US 9,941,207

Granted Patent B2

US 9,941,207 · App. 14/971,627 · Granted Apr 10, 2018

Semiconductor device and method of fabricating 3D package with short cycle time and high yield

Inventor: Yaojian Lin (Singapore, SG)

H01L23/528 H01L21/6835 H01L21/6836 H01L21/76895 H01L21/78 H01L22/20 H01L23/3107 H01L23/49811 H01L24/96 H01L24/97 H01L25/16 H01L25/50 H01L21/561 H01L23/544 H01L24/81 H01L24/83 H01L2221/68327 H01L2221/68331 H01L2221/68359 H01L2221/68372 H01L2221/68381 H01L2223/54433 H01L2223/54486 H01L2224/03334 H01L2224/04105 H01L2224/32225 H01L2224/73253 H01L2224/81005 H01L2224/81191 H01L2224/81192 H01L2224/81815 H01L2224/83005 H01L2224/94 H01L2224/96 H01L2224/97 H01L2924/15311 H01L2924/19104 H01L2924/19105 H01L2924/19106 H01L2924/37001

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Quick Facts

Patent No.: US 9,941,207
App. No.: 14/971,627
Granted: Apr 10, 2018
Kind: B2

External Links

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Abstract

A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

Claims (77)

1. A method of making a semiconductor device, comprising:

providing a first manufacturing line;

providing a second manufacturing line;

forming a first redistribution interconnect structure over a first carrier using the first manufacturing line;

forming a second redistribution interconnect structure over a second carrier using the second manufacturing line;

testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU);

disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure after forming the first redistribution interconnect structure using the first manufacturing line;

dicing the first redistribution interconnect structure and first carrier into KGUs after disposing the KGD over the first redistribution interconnect structure;

testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU);

disposing the first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure after dicing the first redistribution interconnect structure, wherein the KGD is between the first KGU and second KGU;

removing the first carrier and second carrier after disposing the first KGU over the second KGU; and

dicing the second redistribution interconnect structure after disposing the first KGU and KGD over the second KGU.

2. The method of claim 1 , further including:

providing a third manufacturing line;

testing a semiconductor die of a semiconductor wafer to determine the KGD; and

dicing the KGD from the semiconductor wafer using the third manufacturing line.

3. The method of claim 1 , further including:

testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and

disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

4. The method of claim 1 , wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.

5. The method of claim 1 , wherein a resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

6. The method of claim 5 , wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.

7. A method of making a semiconductor device, comprising:

providing a first manufacturing line;

providing a second manufacturing line;

forming a first redistribution interconnect structure using the first manufacturing line;

providing a carrier;

forming a second redistribution interconnect structure over the carrier using the second manufacturing line;

testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU);

disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure after forming the first redistribution interconnect structure;

forming a vertical interconnect structure over the first redistribution interconnect structure adjacent to the KGD;

disposing the first redistribution interconnect structure and KGD over the second redistribution interconnect structure with the KGD and vertical interconnect structure between the first redistribution interconnect structure and second redistribution interconnect structure; and

removing the carrier after disposing the first redistribution interconnect structure and KGD over the second redistribution interconnect structure.

8. The method of claim 7 , further including:

providing a third manufacturing line;

testing a semiconductor die of a semiconductor wafer to determine the KGD; and

dicing the KGD from the semiconductor wafer using the third manufacturing line.

9. The method of claim 7 , further including:

testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and

disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

10. The method of claim 7 , wherein a resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

11. The method of claim 10 , wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.

12. The method of claim 7 , wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.

13. The method of claim 7 , further including:

testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and

disposing the first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

14. A method of making a semiconductor device, comprising:

forming a first redistribution interconnect structure over a carrier using a first manufacturing line;

forming a second redistribution interconnect structure using a second manufacturing line;

disposing a semiconductor die over the first redistribution interconnect structure after forming the first redistribution interconnect structure;

disposing the second redistribution interconnect structure over the first redistribution interconnect structure and semiconductor die with the semiconductor die disposed between the first redistribution interconnect structure and second redistribution interconnect structure; and

removing the carrier after disposing the second redistribution interconnect structure over the first redistribution structure.

15. The method of claim 14 , further including:

testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU);

testing the semiconductor die to determine a known good semiconductor die (KGD); and

disposing the KGD over the first KGU of the first redistribution interconnect structure.

16. The method of claim 15 , further including:

testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and

disposing the first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.

17. The method of claim 16 , further including:

providing a third manufacturing line; and

dicing the KGD from a semiconductor wafer using the third manufacturing line.

18. The method of claim 14 , further including:

testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and

disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

19. The method of claim 14 , wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.

20. The method of claim 14 , wherein a resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

21. The method of claim 20 , wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.

22. A method of making a semiconductor device, comprising:

providing a first build-up interconnect structure;

disposing a semiconductor die over the first build-up interconnect structure;

disposing a vertical interconnect structure over the first build-up interconnect structure adjacent to the semiconductor die;

providing a carrier;

forming a second build-up interconnect structure on the carrier;

disposing the second build-up interconnect structure over the first build-up interconnect structure, vertical interconnect structure, and semiconductor die; and

removing the carrier after disposing the second build-up interconnect structure over the first build-up interconnect structure to expose a contact pad of the second build-up interconnect structure.

23. The method of claim 22 , wherein the semiconductor die is a dummy semiconductor die.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2015

From: LIN, YAOJIAN

To: STATS CHIPPAC, LTD.

Reel/Frame 037309/0211 →

Continuity (3)

Continuation In Part 14887561 · Oct 20, 2015

Provisional Application 62068499 · Oct 24, 2014

Related Publication 20160118333A1 · Apr 28, 2016