IP Library Granted Patent US 9,923,092
Granted Patent B2
US 9,923,092 · App. 14/971,732 · Granted Mar 20, 2018

Method of forming a semiconductor device

Inventors: Thierry Coffi Herve Yao (Portland, OR); Moshe Agam (Portland, OR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L29/7823H01L29/0623H01L29/0878H01L29/1083H01L29/1095H01L29/402H01L29/66681H01L29/7816H01L29/7835
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Quick Facts
Patent No.
US 9,923,092
App. No.
14/971,732
Granted
Mar 20, 2018
Kind
B2
Abstract

In one embodiment, a method of forming a semiconductor device may include forming a buried region within a semiconductor region, including forming an opening in the buried region. The method may also include forming a drift region of a second conductivity type in the semiconductor region with at least a portion of the drift region overlying a first portion of the buried region. Another portion of the method may include forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region.

Claims (23)

1. A method of forming a semiconductor device comprising:

forming a semiconductor region of a first conductivity type overlying a bulk semiconductor substrate;

forming a buried region of the first conductivity type in the semiconductor region;

forming a drift region of a second conductivity type in the semiconductor region with at least a first portion of the drift region overlying a first portion of the buried region, wherein the second conductivity type is opposite to the first conductivity type;

forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region; and

forming an opening in the buried region with the opening underlying the first drain region with a first portion of the buried region extending away from the opening and underlying the first portion of the drift region and a second portion of the buried region extending away from the opening to underlie a source region.

2. The method of claim 1 further including forming a body region of the first conductivity type in the semiconductor region and overlying a second portion of the buried region and spaced apart from the drift region.

3. The method of claim 1 further including forming a second drain region in the first drain region wherein the second drain region does not overlie the buried region.

4. The method of claim 1 further including forming the first drain region to extend a distance into the semiconductor region that is no greater than a depth of a field insulator that is formed adjacent to the first drain region.

5. The method of claim 1 further including forming the first portion of the buried region positioned on one side of the first drain region; and

forming a second portion of the buried region underlying a second portion of the drift region including forming a third portion of the drift region between the first and second portions of the drift regions and separating the first and second portions of the buried region from each other wherein the third portion of the drift region underlies the first drain region.

6. The method of claim 1 further including forming a body region of the first conductivity type in the semiconductor region and spaced laterally apart from the drift region.

7. The method of claim 1 further including forming a doping concentration of the buried region to be greater than a doping concentration of the semiconductor region.

8. The method of claim 1 further including forming a portion of the semiconductor region underlying the buried region and disposed between the buried region and the bulk semiconductor substrate.

9. The method of claim 1 further including forming the semiconductor region to extend through an opening in the buried region and to contact an underlying region of the same conductivity type.

10. The method of claim 1 further including forming the semiconductor region to extend through an opening in the buried region and to contact the bulk semiconductor substrate.

11. A method of forming a semiconductor device comprising:

forming a semiconductor region overlying a bulk semiconductor substrate, the bulk semiconductor substrate having a lateral surface;

forming a buried region of a first conductivity type in the semiconductor region and having an opening within the buried region wherein a first portion of the semiconductor region extends into the opening and a second portion of the semiconductor region extends to underlie at least a portion of the buried region that extends laterally and substantially parallel to the lateral surface of the bulk semiconductor substrate;

forming a drift region of a second conductivity type in the semiconductor region with at least a first portion of the drift region overlying a first portion of the buried region; and

forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region but overlies the opening.

12. The method of claim 11 further including forming the semiconductor region to have the first conductivity type.

13. The method of claim 11 wherein the second portion of the semiconductor region extends to underlie at least twenty percent of the portion of the buried region that extends laterally and substantially parallel to the lateral surface of the bulk semiconductor substrate.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2015
From: YAO, THIERRY COFFI HERVE; AGAM, MOSHE
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 037309/0797 →
Continuity (2)
Division 14275176 · May 12, 2014
Related Publication 20160104796A1 · Apr 14, 2016