IP Library Granted Patent US 9,818,939
Granted Patent B2
US 9,818,939 · App. 14/990,550 · Granted Nov 14, 2017

Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof

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Quick Facts
Patent No.
US 9,818,939
App. No.
14/990,550
Granted
Nov 14, 2017
Kind
B2
Abstract

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Claims (41)

1. A method of forming a resistive switching device, the method comprising:

forming a first insulating layer over a substrate;

forming a first electrode in the first insulating layer;

forming a oxide layer over the first electrode;

forming a tellurium layer over and contacting the oxide layer, wherein the tellurium layer formed over the oxide layer comprises a Group IV element, wherein the Group IV element comprises titanium, zirconium, or hafnium, wherein the tellurium layer with the Group IV element is separated from the first electrode by the oxide layer; and

forming a second electrode disposed over and contacting the tellurium layer.

2. The method of claim 1 , wherein the second electrode comprises less than 5% of copper and silver.

3. The method of claim 1 , further comprising forming a third electrode on the second electrode.

4. The method of claim 1 , wherein the total amount of tellurium by atomic percent in the tellurium layer is 25% to 70%.

5. The method of claim 1 , wherein forming a tellurium layer comprises co-sputtering tellurium with the group IV element, wherein the group IV element comprises titanium, zirconium, or hafnium.

6. The method of claim 5 , wherein the co-sputtering uses different sources for the tellurium and the group IV element.

7. The method of claim 1 , wherein forming a tellurium layer comprises sputtering using a common source for the tellurium and the group IV element.

8. The method of claim 1 , wherein forming a tellurium layer comprises depositing an amorphous layer.

9. The method of claim 1 , wherein forming a tellurium layer comprises depositing a layer comprising tellurium and a layer comprising the group IV element, and repeating the depositing to form a super lattice stack.

10. The method of claim 9 , further comprising annealing the super lattice stack.

11. The method of claim 1 , wherein the tellurium layer comprises 0.1 ppm to 1000 ppm of copper and silver.

12. The method of claim 1 , wherein the oxide layer comprises a metal.

13. A method of forming a resistive switching device, the method comprising:

forming a first insulating layer over a substrate;

forming a first electrode in the first insulating layer;

forming a oxide layer over the first electrode;

forming a tellurium layer over and contacting the oxide layer, wherein the tellurium layer comprises less than 0.01% of copper and silver; and

forming a second electrode disposed over and contacting the tellurium layer, wherein forming a tellurium layer comprises depositing a crystalline layer and amorphising the crystalline layer using implantation.

14. The method of claim 1 , wherein forming a tellurium layer comprises depositing a layer comprising tellurium and a layer comprising the group IV element.

15. The method of claim 14 , further comprising annealing the tellurium layer to form an amorphous layer comprising tellurium and the group IV element.

16. A method of forming a resistive switching device, the method comprising:

forming a first electrode disposed over a substrate

forming a switching layer over the first electrode, the switching layer contacting the first electrode;

forming a conductive amorphous layer over and contacting the switching layer, wherein the conductive amorphous layer comprises tellurium or selenium and a Group IV element, wherein the Group IV element comprises titanium, zirconium, or hafnium, wherein the switching layer is configured to exhibit a first impedance in a first state of the resistive switching device and a second impedance in a second state of the resistive switching device, the second state being different from the first state, wherein the conductive amorphous layer comprises a substantially same impedance in the first state and the second state, wherein the switching layer separates the first electrode from the conductive amorphous layer with the Group IV element; and

forming a second electrode over the conductive amorphous layer, wherein the second electrode is disposed over and contacts the conductive amorphous layer.

17. The method of claim 16 , wherein the first electrode is a metal silicide.

18. The method of claim 16 , wherein the first electrode comprises tungsten, tantalum, or molybdenum.

19. The method of claim 16 , wherein the conductive amorphous layer further comprises a transitional metal.

20. The method of claim 16 , wherein the conductive amorphous layer further comprises a rare earth metal.

21. The method of claim 16 , wherein the conductive amorphous layer comprises tellurium.

22. The method of claim 16 , wherein the ratio of the number of Group IV element atoms to the number of tellurium atoms in the conductive amorphous layer is between 0.5:1 to 3:1.

23. The method of claim 16 , wherein the switching layer comprises gadolinium oxide, aluminum oxide, hafnium oxide, zirconium oxide, silicon oxide, or mixtures thereof.

24. The method of claim 16 , wherein the conductive amorphous layer comprises less than 0.01% of copper and silver, wherein the second electrode comprises less than 5% of copper and silver, wherein the switching layer comprises less than 0.01% of copper and silver.

25. The method of claim 16 , wherein the conductive amorphous layer comprises selenium.

26. The method of claim 16 , wherein the second electrode comprises an element selected from tantalum, tungsten, and molybdenum.

27. The method of claim 16 , wherein the conductive amorphous layer comprises 0.1 ppm to 1000 ppm of copper and silver.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: RENESAS DESIGN US INC. (FORMERLY KNOWN AS DIALOG SEMICONDUCTOR US INC. AS SUCCESSOR-IN-INTEREST TO ADESTO TECHNOLOGIES CORPORATION AND ARTEMIS ACQUISITION, LLC)
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 063118/0352 →
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →