IP Library Granted Patent US 10,784,205
Granted Patent B2
US 10,784,205 · App. 14/990,933 · Granted Sep 22, 2020

Electronic package

Inventors: Chu-Chin Hu (Hsinchu County, TW); Shih-Ping Hsu (Hsinchu County, TW)
Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
H01L23/5389G06K9/0004H01L27/14618H05K1/185H01L2224/18H01L2224/45144H01L2224/48091H01L2224/48227H01L2224/48465H01L2924/15311H01L2924/16235H01L2924/181H05K3/284H05K2201/10H05K2201/10121H05K2201/10151
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Quick Facts
Patent No.
US 10,784,205
App. No.
14/990,933
Granted
Sep 22, 2020
Kind
B2
Abstract

An electronic package is provided, which includes: an insulating layer; an electronic element embedded in the insulating layer and having a sensing area exposed from the insulating layer; and a circuit layer formed on the insulating layer and electrically connected to the electronic element, thereby reducing the thickness of the overall package structure.

Claims (27)

1. An electronic package, comprising:

a first insulating layer having opposite first and second surfaces;

an electronic element embedded in the first insulating layer and having an active surface with at least a sensing area and a plurality of electrode pads exposed from the first surface of the first insulating layer and an inactive surface opposing the active surface;

a first circuit layer formed on the first surface of the first insulating layer, wherein the first circuit layer is in contact with the electrode pads and in electrical connection with the electronic element, and the sensing area is exposed from the first circuit layer;

a second circuit layer embedded in the second surface of the first insulating layer and electrically connected to the first circuit layer, wherein the second circuit layer is in contact with a part of the inactive surface of the electronic element and free from being in contact with corner portions of the inactive surface of the electronic element; and

a plurality of solid conductive posts embedded in the first insulating layer and electrically connected to the first circuit layer and the second circuit layer, wherein the solid conductive posts are in direct contact with the first circuit layer and the second circuit layer.

2. The electronic package of claim 1 , further comprising a second insulating layer formed on the first surface of the first insulating layer and the first circuit layer, wherein the sensing area is exposed from the second insulating layer.

3. The electronic package of claim 2 , wherein portions of the first circuit layer are exposed from the second insulating layer.

4. The electronic package of claim 1 , further comprising a third insulating layer formed on the second surface of the first insulating layer and the second circuit layer.

5. The electronic package of claim 4 , wherein portions of the second circuit layer are exposed from the third insulating layer.

6. The electronic package of claim 1 , further comprising a plurality of conductive elements formed on the second surface of the first insulating layer.

7. The electronic package of claim 1 , further comprising a redistribution layer (RDL) structure disposed on the second surface of the first insulating layer and electrically connected to the first circuit layer.

8. The electronic package of claim 1 , further comprising a transparent element covering the sensing area of the electronic element.

9. An electronic package, comprising:

a first insulating layer having opposite first and second surfaces;

an electronic element embedded in the first insulating layer and having an active surface with at least a sensing area and a plurality of electrode pads exposed from the first surface of the first insulating layer and an inactive surface opposing the active surface;

a first circuit layer formed on the first surface of the first insulating layer, wherein the first circuit layer is in contact with the electrode pads and in electrical connection with the electronic element, and the sensing area is exposed from the first circuit layer;

a second circuit layer embedded in the second surface of the first insulating layer and electrically connected to the first circuit layer, wherein the second circuit layer is in contact with a part of the inactive surface of the electronic element and free from being in contact with corner portions of the inactive surface of the electronic element;

a plurality of solid conductive posts embedded in the first insulating layer and electrically connected to the first circuit layer and the second circuit layer, wherein the solid conductive posts are in direct contact with the first circuit layer and the second circuit layer; and

a second insulating layer covering the sensing area of the electronic element.

10. The electronic package of claim 9 , further comprising a third insulating layer formed on the second surface of the first insulating layer and the second circuit layer.

11. The electronic package of claim 10 , wherein portions of the second circuit layer are exposed from the third insulating layer.

12. The electronic package of claim 9 , further comprising a plurality of conductive elements formed on the second surface of the first insulating layer.

13. The electronic package of claim 9 , wherein the second insulating layer is further formed on the first surface of the first insulating layer and the first circuit layer.

14. The electronic package of claim 13 , wherein portions of the first circuit layer are exposed from the second insulating layer.

15. The electronic package of claim 9 , further comprising a redistribution layer (RDL) structure formed on the second surface of the first insulating layer and electrically connected to the first circuit layer.

16. The electronic package of claim 9 , further comprising a transparent element covering the sensing area of the electronic element.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED ON REEL 037436 FRAME 0946. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2016
From: HU, CHU-CHIN; HSU, SHIH-PING
To: PHOENIX PIONEER TECHNOLOGY CO., LTD.
Reel/Frame 038716/0595 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2016
From: HU, CHU-CHIN; HSU, SHIH-PING
To: PHOENIX PIONEER TECHNOLOGY CO., LTD.
Reel/Frame 037436/0946 →
Priority Claims (1)
CN 2015 1 0022806 · Jan 16, 2015 · national
Continuity (1)
Related Publication 20160212852A1 · Jul 21, 2016
Cited By (1)
US 12,628,449