High performance multiplexed latches

1. A multiplexed latch comprising:

a first latch structured to receive a data signal D 0 and comprising a plurality of inverters which receive a respective input clock signal; and

a second latch structured to receive a data signal D 1 and comprising a plurality of inverters which receive a respective input clock signal,

wherein the plurality of inverters of the second latch comprises a feedback inverter in parallel with a driving inverter, and a first inverter in series with the driving inverter, and

in the second latch:

an input clock signal CLK 1 is an input to the first inverter;

an input clock signal CLK 1 N is an input to the feedback inverter; and

an input clock signal CLK 0 N is an input to the driving inverter.

2. The multiplexed latch of claim 1 , wherein the plurality of input clock signals for the first latch and the second latch comprise three clock signals for inputting into respective inverters for each of the first latch and the second latch.

3. The multiplexed latch of claim 2 , wherein:

the plurality of input clock signals for the first latch comprises CLK 0 , CLK 0 N and CLK 1 N.

4. The multiplexed latch of claim 3 , wherein the input clock signal CLK 0 N is an inverted signal of the input clock signal CLK 0 and the input clock signal CLK 1 N is an inverted signal of the input clock signal CLK 1 .

5. The multiplexed latch of claim 4 , wherein the plurality of inverters of the first latch comprise a feedback inverter in parallel with a driving inverter, and a first inverter in series with the driving inverter.

6. The multiplexed latch of claim 5 , wherein:

in the first latch:

the input clock signal CLK 0 is an input to the first inverter;

the input clock signal CLK 0 N is an input to the feedback inverter; and

the input clock signal CLK 1 N is an input to the driving inverter.

7. The multiplexed latch of claim 5 , wherein, when the input clock signal CLK 0 goes high the data signal D 0 is enabled to pass through the first inverter of the first latch, the input clock signal CLK 0 N goes low and isolates the second latch and the first latch drives output data Q.

8. The multiplexed latch of claim 5 , wherein, when the input clock signal CLK 1 goes high the data signal D 0 is enabled to pass through the first inverter of the second latch, the input clock signal CLK 1 N goes low and isolates the first latch and the second latch drives output data Q.

9. A multiplexed latch comprising:

a first latch comprising:

a first inverter which is structured to receive a data signal D 0 and an input clock signal CLK 0 ;

a driving inverter in series with the first inverter and which is structured to receive an input clock signal CLK 1 N;

a feedback inverter which is parallel to the driving inverter and which is structured to receive an input clock signal CLK 0 N; and

a second latch comprising:

a first inverter which is structured to receive a data signal D 1 and an input clock signal CLK 1 ;

a driving inverter in series with the first inverter and which is structured to receive the input clock signal CLK 0 N; and

a feedback inverter which is parallel to the driving inverter and which is structured to receive the input clock signal CLK 1 N.

10. The multiplexed latch of claim 9 , wherein the input clock signal CLK 0 N is an inverted signal of the input clock signal CLK 0 and the input clock signal CLK 1 N is an inverted signal of the input clock signal CLK 1 .

11. The multiplexed latch of claim 10 , wherein, when the input clock signal CLK 0 goes high and the data signal D 0 is enabled, the input clock signal CLK 0 N goes low and isolates the second latch, and the first latch drives output data Q.

12. The multiplexed latch of claim 11 , wherein, when the input clock signal CLK 0 goes high, the driving inverter of the second latch is low, the feedback inverter of the first latch is low and the driving inverter of the first latch is high, driving the output data Q.

13. The multiplexed latch of claim 10 , wherein, when the input clock signal CLK 0 goes low and the data signal D 0 is enabled, the driving inverter of the second latch is high, the feedback inverter of the first latch is high and the driving inverter of the first latch is low, and the output data Q is driven through both the first latch and the second latch.

14. The multiplexed latch of claim 10 , wherein, when the input clock signal CLK 1 goes high and the data signal D 1 is enabled, the input clock signal CLK 1 N goes low and isolates the first latch, and the second latch drives output data Q.

15. The multiplexed latch of claim 14 , wherein, when the input clock signal CLK 1 goes high and the data signal D 1 is enabled, the driving inverter of the first latch is low, the feedback inverter of the second latch is low and the driving inverter of the second latch is high, driving the output data Q.

16. The multiplexed latch of claim 10 , wherein, when the input clock signal CLK 1 goes low and the data signal D 1 is enabled, the driving inverter of the first latch is high, the feedback inverter of the second latch is high and the driving inverter of the second latch is low, and the output data Q is driven through both the first latch and the second latch.

17. The multiplexed latch of claim 10 , wherein the input clock signal CLK 1 N and the input clock signal CLK 0 N are enabled by a SEL signal.

18. A method comprising:

enabling an input signal into a first inverter of a first latch to drive output data through a driving inverter of the first latch while turning off a feedback inverter of the first latch and isolating a second latch;

enabling an input signal into a first inverter of the second latch to drive output data through a driving inverter of the second latch while turning off a feedback inverter of the second latch and isolating the first latch, wherein:

the first inverter of the first latch receives a data signal D 0 and an input clock signal CLK 0 ;

the driving inverter of the first latch receives an input clock signal CLK 1 N,

the feedback inverter of the first latch receives an input clock signal CLK 0 N;

the first inverter of the second latch receives a data signal D 1 and an input clock signal CLK 1 ;

the driving inverter of the second latch receives the input clock signal CLK 0 N; and

the feedback inverter of the second latch receive the input clock signal CLK 1 N.