Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
1. A ferroelectric field effect transistor, comprising:
a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;
a source/drain region at opposite ends of the channel; and
a gate construction comprising:
inner dielectric extending along the channel top and laterally along the channel sidewalls;
inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;
outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top;
outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top; and
all of the outer conductive material, the outer ferroelectric material, and the inner conductive material having at least two pairs of two laterally opposing vertical sidewalls elevationally outward of the channel that are laterally coincident relative one another.
2. A ferroelectric field effect transistor, comprising:
a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;
a source/drain region at opposite ends of the channel; and
a gate construction comprising:
inner dielectric extending along the channel top and laterally along the channel sidewalls;
inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;
outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top;
outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top; and
the outer ferroelectric material and the inner conductive material having respective encircling perimeter edges in at least one respective horizontal cross section elevationally outward of the channel that are everywhere laterally coincident.
3. A ferroelectric field effect transistor, comprising:
a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;
a source/drain region at opposite ends of the channel; and
a gate construction comprising:
inner dielectric extending along the channel top and laterally along the channel sidewalls;
inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;
outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top;
outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top; and
the outer ferroelectric material and the outer conductive material having respective encircling perimeter edges in at least one respective horizontal cross section elevationally outward of the channel that are everywhere laterally coincident.
4. A ferroelectric field effect transistor, comprising:
a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;
a source/drain region at opposite ends of the channel; and
a gate construction comprising:
inner dielectric extending along the channel top and laterally along the channel sidewalls;
inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;
outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top;
outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top; and
the inner conductive material and the outer conductive material having respective encircling perimeter edges in at least one respective horizontal cross section elevationally outward of the channel that are everywhere laterally coincident.
5. The ferroelectric field effect transistor of claim 4 wherein the outer ferroelectric material has an encircling perimeter edge in at least one horizontal cross section elevationally outward of the channel that is everywhere laterally coincident with said encircling perimeter edges of the inner and outer conductive materials.
6. A plurality of ferroelectric field effect transistors arrayed in row lines and column lines, comprising:
individual ferroelectric field effect transistors comprising:
a semiconductive channel comprising opposing sidewalls and an elevationally outermost top;
a source/drain region at opposite ends of the channel; and
a gate construction comprising:
inner dielectric extending along the channel top and laterally along the channel sidewalls;
inner conductive material elevationally and laterally outward of the inner dielectric and extending along the channel top and laterally along the channel sidewalls;
outer ferroelectric material elevationally outward of the inner conductive material and extending along the channel top; and
outer conductive material elevationally outward of the outer ferroelectric material and extending along the channel top;
at least one of the outer conductive material and the outer ferroelectric material being discontinuous along both of the row lines and the column lines between immediately adjacent ferroelectric field effect transistors; and
both of the outer conductive material and the outer ferroelectric material being discontinuous along both of the row lines and the column lines between immediately adjacent ferroelectric field effect transistors.
7. The ferroelectric field effect transistors of claim 6 wherein the outer conductive material and the outer ferroelectric material have at least two pairs of two laterally opposing vertical sidewalls elevationally outward of the channel that are laterally coincident.