IP Library Granted Patent US 9,768,255
Granted Patent B2
US 9,768,255 · App. 15/006,717 · Granted Sep 19, 2017

Semiconductor devices including contact structures that partially overlap silicide layers

Inventors: Do-Sun Lee (Suwon-si, KR); Chang-Woo Sohn (Hwaseong-si, KR); Chul-Sung Kim (Seongnam-si, KR); Shigenobu Maeda (Seongnam-si, KR); Young-Moon Choi (Seoul, KR); Hyo-Seok Choi (Hwaseong-si, KR); Sang-Jin Hyun (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L29/0847H01L29/0653H01L29/161H01L29/165H01L29/41791H01L29/785H01L29/7848
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Quick Facts
Patent No.
US 9,768,255
App. No.
15/006,717
Granted
Sep 19, 2017
Kind
B2
Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Claims (52)

1. A semiconductor device comprising:

a substrate;

an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction;

an epitaxial layer on the active portions;

a metal silicide layer on the epitaxial layer; and

a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer, wherein:

the epitaxial layer comprises a plurality of epitaxial patterns on respective ones of the active portions of the substrate;

each of the plurality of epitaxial patterns comprises a polygonal shape; and

the metal silicide layer is on a plurality of sides of the polygonal shape of each of the plurality of epitaxial patterns.

2. The device of claim 1 , further comprising an insulating interlayer on the metal silicide layer, wherein the contact structure is in a contact hole in the insulating interlayer.

3. The device of claim 2 , wherein the contact structure is on less than half of an entire uppermost surface of the metal silicide layer.

4. The device of claim 2 , wherein a first thickness of a first portion of the metal silicide layer underlying the contact structure is thinner than a second thickness of a second portion of the metal silicide layer underlying the insulating interlayer.

5. The device of claim 1 , wherein:

the epitaxial layer comprises an epitaxial source/drain region of a fin-shaped Field Effect Transistor (FinFET); and

the metal silicide layer is on the epitaxial source/drain region.

6. The device of claim 1 , wherein the direction in which the active portions of the substrate are spaced apart comprises a first direction, the device further comprising metal gate structures that are spaced part from each other in a second direction on an active fin structure.

7. The device of claim 1 , wherein the metal silicide layer is on at least three sides of the polygonal shape of each of the plurality of epitaxial patterns.

8. The device of claim 1 , wherein the metal silicide layer is on at least five sides of the polygonal shape of each of the plurality of epitaxial patterns.

9. The device of claim 1 , wherein:

the plurality of epitaxial patterns comprise respective first through third ones of the polygonal shapes; and

the second polygonal shape contacts each of the first and third polygonal shapes.

10. The device of claim 1 , wherein:

the plurality of epitaxial patterns comprise gaps therebetween; and

the metal silicide layer electrically connects the plurality of epitaxial patterns with each other.

11. The device of claim 1 , wherein the contact structure overlaps only one of the plurality of epitaxial patterns.

12. The device of claim 1 , wherein:

the direction in which the active portions of the substrate are spaced apart comprises a first direction;

the epitaxial layer comprises a first plurality of epitaxial patterns and a second plurality of epitaxial patterns that is spaced apart from the first plurality of epitaxial patterns in a second direction; and

the contact structure comprises first and second contact structures on the first plurality of epitaxial patterns and the second plurality of epitaxial patterns, respectively.

13. The device of claim 12 , wherein the first and second contact structures are in a pattern that defines an acute angle with the second direction.

14. A semiconductor device comprising:

a substrate;

an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction;

an epitaxial layer on the active portions;

a metal silicide layer on the epitaxial layer; and

a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer, wherein:

the direction in which the active portions of the substrate are spaced apart comprises a first direction;

the epitaxial layer comprises first through third pluralities of epitaxial patterns that are spaced apart from each other in a second direction; and

the contact structure comprises first through third contact structures on the first through third pluralities of epitaxial patterns, respectively, and are at different positions from each other in the first direction when viewed in a plan view.

15. The device of claim 14 , wherein the first through third contact structures on the first through third pluralities of epitaxial patterns, respectively, define a zig-zag pattern when viewed in the plan view.

16. The device of claim 1 , further comprising a metal gate structure,

wherein the epitaxial layer comprises first and second epitaxial source/drain patterns on first and second sides, respectively, of the metal gate structure.

17. The device of claim 1 , wherein the metal silicide layer extends to a portion of the epitaxial layer that is spaced apart from the contact structure.

18. A semiconductor device comprising:

a substrate comprising a plurality of fin-shaped patterns;

a plurality of metal gate structures on respective ones of the plurality of fin-shaped patterns;

a plurality of epitaxial source/drain patterns on the plurality of fin-shaped patterns;

a plurality of metal silicide layers on respective ones of the plurality of epitaxial source/drain patterns, wherein each of the metal silicide layers extends continuously from a first portion of its respective epitaxial source/drain pattern that is on a first of the plurality of fin-shaped patterns to a second portion of its respective epitaxial source/drain pattern that is on a second of the plurality of fin-shaped patterns; and

a plurality of contact structures on, and only partially overlapping, respective ones of the plurality of metal silicide layers.

19. The device of claim 18 , wherein:

the plurality of metal silicide layers are on entireties of surface areas of respective uppermost surfaces of the plurality of epitaxial source/drain patterns; and

the plurality of contact structures are on less than half of surface areas of respective uppermost surfaces of the plurality of metal silicide layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2016
From: LEE, DO-SUN; SOHN, CHANG-WOO; KIM, CHUL-SUNG; MAEDA, SHIGENOBU; CHOI, YOUNG-MOON; CHOI, HYO-SEOK; HYUN, SANG-JIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037587/0066 →
Priority Claims (1)
KR 10-2015-0052355 · Apr 14, 2015 · national
Continuity (1)
Related Publication 20160308004A1 · Oct 20, 2016