Memory built-in self test system
A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.
1. A memory built-in self test (“BIST”) system, comprising:
a controller for generating test instructions based on received operation codes (“op-codes”) for testing a plurality of memory types, wherein the controller comprises a microcontroller, an interface for receiving the op-codes to program the microcontroller with the test instructions, and an input/output (“IO”) block;
a single port memory BIST engine coupled to one or more single port memories, wherein the single port memory BIST engine comprises a first data generator, a first command generator, and a first address generator; and
a non-single port memory BIST engine coupled to one or more non-single port memories, wherein the non-single port memory BIST engine comprises a second data generator, a second command generator, and a second address generator,
wherein an output of the controller is coupled to inputs of the single port memory BIST engine and the non-single port memory BIST engine for inputting the test instructions to
the single port memory BIST engine and the non-single port memory BIST engine to test the one or more single port memories and the one or more non-single port memories.
2. The memory BIST system of claim 1 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, a reserved field, an operation type field, an operation disable field, a special modifier field, and a data field, wherein the control field supports looping across one or more of the op-codes, and wherein the special modifier field supports looping within operations of a certain one or more of the op-codes.
3. The memory BIST system of claim 2 wherein the certain ones of the op-codes are used to generate certain test instructions for the single port memories and the non-single port memories.
4. The memory BIST system of claim 1 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, an operation type field, a search expect/data valid field, an operation disable field, a special modifier field, and a data field, wherein the control field supports looping across one or more of the op-codes, and wherein the special modifier field supports looping within operations of a certain one or more of the op-codes.
5. The memory BIST system of claim 4 wherein the certain ones of the op-codes are used to generate certain test instructions for ternary content addressable memories.
6. The memory BIST system of claim 1 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, an operation type A port field, an operation type B port field, a data A port field, an operation disable port field, a special modifier field, and a data B port field, wherein the control field supports looping across one or more of the op-codes, and wherein the special modifier field supports looping within operations of a certain one or more of the op-codes.
7. The memory BIST system of claim 6 wherein the certain ones of the op-codes are used to generate certain test instructions for multi-port memories.
8. A memory built-in self test (“BIST”) system, comprising:
a controller, wherein the controller receives operation codes (“op-codes”) for testing a plurality of memory types, wherein the controller comprises a microcontroller, an interface, and an input/output (“IO”) block, and wherein the interface receives the op-codes to program the microcontroller with the test instructions;
a single port memory engine coupled to one or more single port memories, wherein the single port memory engine comprises a first data generator, a first command generator, and a first address generator;
a ternary content addressable memory (“TCAM”) engine coupled to one or more TCAMs, wherein the TCAM engine comprises a second data generator, a second command generator, and a second address generator; and
a multi-port memory engine coupled to one or more multi-port memories, wherein the multi-port memory engine comprises a third data generator, a third command generator, and a third address generator,
wherein the test instructions are outputted to the single port memory engine, the TCAM engine, and the multi-port memory engine via the IO block,
wherein an output of the controller is coupled to inputs of the single port memory engine, the TCAM engine, and the multi-port memory engine,
wherein the controller generates test instructions based on the received op-codes, and wherein the single port memory engine, the TCAM engine, and the multi-port memory engine interpret the test instructions to test the one or more single port memories, the one or more TCAMs, and the one or more multi-port memories.
9. The memory BIST system of claim 8 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, a reserved field, an operation type field, an operation disable field, a special modifier field, and a data field, wherein the control field supports looping across one or more of the op-codes, wherein the special modifier field supports looping within operations of a certain one or more of the op-codes, and wherein the certain ones of the op-codes are used to generate certain test instructions for the single port memories and the multi-port memories.
10. The memory BIST system of claim 8 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, an operation type field, a search expect/data valid field, an operation disable field, a special modifier field, and a data field, wherein the control field supports looping across one or more of the op-codes, wherein the special modifier field supports looping within operations of a certain one or more of the op-codes, and wherein the certain ones of the op-codes are used to generate certain test instructions for the TCAMs.
11. The memory BIST system of claim 8 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, an operation type A port field, an operation type B port field, a data A port field, an operation disable port field, a special modifier field, and a data B port field, wherein the control field supports looping across one or more of the op-codes, wherein the special modifier field supports looping within operations of a certain one or more of the op-codes, and wherein the certain ones of the op-codes are used to generate certain test instructions for the multi-port memories.
12. A method for a memory built-in self test (“BIST”), comprising the steps of:
loading operation codes (“op-codes”) to an interface of a controller;
generating test instructions based on the loaded op-codes;
outputting the test instructions to a single port memory BIST engine and a non-single port memory BIST engine via an input/output (“I/O”) block of the controller;
interpreting the test instructions and testing by one of the single port memory BIST engine and the non-single port memory BIST engine; and
interpreting the test instructions and testing by another one of the single port memory BIST engine and the non-single port memory BIST engine.
13. The method for the BIST of claim 12 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, a reserved field, an operation type field, an operation disable field, a special modifier field, and a data field, wherein the control field supports looping across one or more of the op-codes, and wherein the special modifier field supports looping within operations of a certain one or more of the op-codes.
14. The method for the BIST of claim 13 wherein the certain ones of the op-codes are used to generate certain test instructions for one or more single port memories and one or more non-single port memories.
15. The method for the BIST of claim 12 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, an operation type field, a search expect/data valid field, an operation disable field, a special modifier field, and a data field, wherein the control field supports looping across one or more of the op-codes, and wherein the special modifier field supports looping within operations of a certain one or more of the op-codes.
16. The method for the BIST of claim 15 wherein the certain ones of the op-codes are used to generate certain test instructions for ternary content addressable memories.
17. The method for the BIST of claim 12 wherein certain ones of the op-codes comprise the following fields: a control field, an address direction field, an operation type A port field, an operation type B port field, a data A port field, an operation disable port field, a special modifier field, and a data B port field, wherein the control field supports looping across one or more of the op-codes, and wherein the special modifier field supports looping within operations of a certain one or more of the op-codes.
18. The method for the BIST of claim 17 wherein the certain ones of the op-codes are used to generate certain test instructions for multi-port memories.