Semiconductor structures including dielectric materials having differing removal rates
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
1. A semiconductor structure, comprising:
a stack of alternating oxide materials and control gates, each of the oxide materials of the stack comprising at least two oxide portions of different densities;
charge storage structures laterally adjacent to the control gates, the charge storage structures comprising a uniform height across a length thereof and no portion of the control gates overlying or underlying the charge storage structures, and each of the charge storage structures having the same height as the respective laterally adjacent control gate;
a charge block material between each of the charge storage structures and the respective laterally adjacent control gate; and
a pillar extending through the stack of alternating oxide materials and control gates.
2. The semiconductor structure of claim 1 , wherein a density of one oxide portion in the at least two oxide portions is from about six times lower to about two times higher than a density of an adjacent oxide portion in the at least two oxide portions.
3. The semiconductor structure of claim 1 , wherein at least some of the oxide materials of the at least two oxide portions comprise a top oxide portion, a middle oxide portion and a bottom oxide portion, and a density of the top oxide portion is substantially equal to a density of the bottom oxide portion and lower than a density of the middle oxide portion.
4. The semiconductor structure of claim 1 , wherein at least some of the oxide materials of the at least two oxide portions comprise a top oxide portion, a middle oxide portion and a bottom oxide portion, and a density of the middle oxide portion is higher than a density of the top oxide portion and a density of the bottom oxide portion.
5. The semiconductor structure of claim 1 , wherein the pillar comprises conductively doped polysilicon.
6. The semiconductor structure of claim 1 , wherein the charge block material comprises an oxide-nitride-oxide (ONO) material.
7. The semiconductor structure of claim 1 , wherein at least some of the oxide materials of the at least two oxide portions comprise a top oxide portion, a middle oxide portion and a bottom oxide portion, and a density of the top oxide portion is different from a density of the bottom oxide portion and lower than a density of the middle oxide portion.
8. The semiconductor structure of claim 1 , wherein at least some of the oxide materials of the at least two oxide portions comprise a top oxide portion, a middle oxide portion and a bottom oxide portion, and a density of the top oxide portion is different from a density of the bottom oxide portion and higher than a density of the middle oxide portion.
9. The semiconductor structure of claim 1 , wherein at least some of the oxide materials of the at least two oxide portions comprise a top oxide portion, a middle oxide portion and a bottom oxide portion, and a density of the top oxide portion is substantially equal to a density of the bottom oxide portion and higher than a density of the middle oxide portion.
10. A semiconductor structure, comprising:
a stack of alternating dielectric materials and control gates, the dielectric materials of the stack comprising a top portion, a middle portion and a bottom portion, the top and bottom portions having lower densities than the middle portion;
a charge storage structure having the same height as the height of an adjacent control gate;
a charge block material between the charge storage structure and the adjacent control gate; and
a channel material extending through the stack of alternating dielectric materials and control gates.
11. The semiconductor structure of claim 10 , wherein the dielectric material is selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
12. The semiconductor structure of claim 10 , further comprising a tunnel dielectric material between the channel material and the charge storage structure.
13. The semiconductor structure of claim 10 , wherein the top and bottom portions of the dielectric material have substantially the same density.
14. The semiconductor structure of claim 10 , wherein the structure comprises a three-dimensional NAND flash memory device.
15. A semiconductor structure, comprising:
a stack of alternating dielectric materials and control gates, each of the dielectric materials of the stack comprising at least two portions of materials formulated to have different rates of removal when exposed to the same etch chemistry and all horizontal surfaces of the control gates in direct contact with the dielectric materials;
charge storage structures laterally adjacent to the control gates, each of the charge storage structures having the same height as the height of a laterally adjacent control gate;
a charge block material between each of the charge storage structures and its laterally adjacent control gate; and
a pillar extending through the stack of alternating dielectric materials and control gates.
16. The semiconductor structure of claim 15 , wherein each of the dielectric materials of the stack comprises at least a first material portion and a second material portion, the first material portion formulated to have an etch rate at least about two times greater than that of the second material portion when exposed to the same etch chemistry.
17. The semiconductor structure of claim 15 , wherein the at least two portions of materials of the stack comprise a material selected from the group consisting of a silicon oxide (SiO x ) material, a silicon nitride (SiN y ) material, a silicon oxynitride (SiO x N y ) material, and combinations thereof.
18. The semiconductor structure of claim 15 , wherein at least some of the dielectric materials of the stack comprise a top material portion, a middle material portion and a bottom material portion, wherein the top material portion has substantially the same rate of removal as the bottom material portion and a higher rate of removal than that of the middle material portion when exposed to the same etch chemistry.
19. The semiconductor structure of claim 18 , wherein the top material portion and bottom material portion comprise a silicon oxide (SiO x ) material, and the middle material portion comprises a silicon nitride (SiN y ) material.
20. The semiconductor structure of claim 18 , wherein the top material portion and bottom material portion comprise a silicon oxide (SiO x ) material, and the middle material portion comprises a silicon oxynitride (SiO x N y ) material.