IP Library Granted Patent US 9,673,109
Granted Patent B2
US 9,673,109 · App. 15/019,318 · Granted Jun 6, 2017

Method for fabricating a semiconductor package with conductive carrier integrated heat spreader

Inventors: Eung San Cho (Torrance, CA); Andrew N. Sawle (East Grinstead, GB); Mark Pavier (Felbridge, GB); Daniel Cutler (Betchworth, GB)
Assignee: Infineon Technologies Americas Corp.
H01L21/84H01L21/4825H01L21/4871H01L21/561H01L23/3121H01L23/49562H01L23/49568H01L23/49575H01L24/24H01L24/32H01L24/73H01L24/82H01L24/83H01L24/92H01L25/072H01L25/117H01L25/16H01L25/18H01L25/50H01L24/16H01L24/29H01L2224/16245H01L2224/24137H01L2224/24245H01L2224/2929H01L2224/29101H01L2224/32245H01L2224/73259H01L2224/73267H01L2224/8382H01L2224/8384H01L2224/92224H01L2224/92244H01L2924/1033H01L2924/10253H01L2924/10323H01L2924/10325H01L2924/10334H01L2924/10341H01L2924/10344H01L2924/10346H01L2924/10355H01L2924/10356H01L2924/10357H01L2924/10358H01L2924/12042H01L2924/1306H01L2924/13091H01L2924/1426H01L2924/1815
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Quick Facts
Patent No.
US 9,673,109
App. No.
15/019,318
Granted
Jun 6, 2017
Kind
B2
Abstract

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Claims (32)

1. A method for fabricating a semiconductor package, said method comprising:

providing a conductive carrier having a die side and an opposite input/output (I/O) side;

providing a control FET and a sync FET of a power converter switching stage, said control FET having a control drain and said sync FET having a sync source;

attaching said control drain of said control FET and said sync source of said sync FET to said die side of said conductive carrier;

forming a control conductive carrier attached to said control drain and a sync conductive carrier attached to said sync source.

2. The method of claim 1 , wherein said conductive carrier comprises a lead frame.

3. The method of claim 1 , wherein said conductive carrier is pre-patterned.

4. The method of claim 1 , wherein said control FET and said sync FET comprise silicon FETs.

5. The method of claim 1 , wherein said control FET and said sync FET comprise III-Nitride FETs.

6. The method of claim 1 , wherein said power converter switching stage is a part of a buck converter.

7. A method for fabricating a semiconductor package, said method comprising:

providing a conductive carrier having a die side and an input/output (I/O) side;

providing a control FET and a sync FET, said control FET having a control drain and said sync FET having a sync source;

attaching said control drain of said control FET and said sync source of said sync FET to said die side of said conductive carrier;

forming a control conductive carrier attached to said control drain.

8. The method of claim 7 , wherein said conductive carrier comprises a lead frame.

9. The method of claim 7 , wherein said conductive carrier is pre-patterned.

10. The method of claim 7 , wherein said control FET and said sync FET comprise silicon FETs.

11. The method of claim 7 , wherein said control FET and said sync FET comprise III-Nitride FETs.

12. The method of claim 7 , wherein said control FET and said sync FET are part of a power converter switching stage.

13. The method of claim 12 , wherein said power converter switching stage is part of a buck converter.

14. A method for fabricating a semiconductor package, said method comprising:

providing a conductive carrier having a die side and an input/output (I/O) side;

providing a control FET and a sync FET, said control FET having a control drain and said sync FET having a sync source;

attaching said control drain of said control FET and said sync source of said sync FET to said die side of said conductive carrier;

forming a sync conductive carrier attached to said sync source.

15. The method of claim 14 , wherein said conductive carrier comprises a lead frame.

16. The method of claim 14 , wherein said conductive carrier is pre-patterned.

17. The method of claim 14 , wherein said control FET and said sync FET comprise silicon FETs.

18. The method of claim 14 , wherein said control FET and said sync FET comprise III-Nitride FETs.

19. The method of claim 14 , wherein said control FET and said sync FET are part of a power converter switching stage.

20. The method of claim 19 , wherein said power converter switching stage is part of a buck converter.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2016
From: CHO, EUNG SAN; SAWLE, ANDREW N.; PAVIER, MARK; CUTLER, DANIEL
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 038649/0739 →
CHANGE OF NAME Recorded May 19, 2016
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 038649/0820 →
Continuity (4)
Continuation 14825382 · Aug 13, 2015
Division 14022584 · Sep 10, 2013
Provisional Application 61715737 · Oct 18, 2012
Related Publication 20160155674A1 · Jun 2, 2016