Image sensor with control signal sequence generation
The invention relates to image sensors and more specifically the generation of control signals for pixels and readout circuits. The sequencing circuit which produces these signals comprises: a programmable memory (MEM) containing binary words (M 0 , M 1 , M 2 , etc.) in which each word comprises a group of several bits of position 1 to N, and in which the position i of a bit in a word corresponds to the position i of a respective control signal; a memory controller (CTRL_MEM) for extracting from the memory at a determined rate the words located at successive addresses of the memory from a start address to an end address; and a control signal generation circuit (GEN_TIMING) establishing each control signal of position i from the succession of bits of respective position i that are extracted from the memory by the controller, the control signal reproducing the successive values taken by the bit of position i at the clock rate.
1. An image sensor comprising a matrix of rows and columns of active pixels, readout circuits, and a sequencing circuit for applying control signals to the pixels and/or to the readout circuits according to clearly determined sequences, wherein the sequencing circuit comprises:
a programmable addressable memory containing binary words in which each word comprises a group of several bits of position 1 to N, and in which the position i of a bit in a word corresponds to the position i of a respective control signal from among a series of control signals for pixels and/or readout circuits of the sensor,
a memory controller for extracting from the memory at a fixed clock rate the words located at successive addresses of the memory from a start address to an end address, which define respectively the beginning and the end of an operational sequence of the image sensor,
and a control signal generation circuit establishing each control signal of position i from the succession at the fixed clock rate of bits of respective position i that are extracted from the memory by the controller, the control signal having a first value or a second value according to the value of the bit and changing value when the bit changes value.
2. The image sensor according to claim 1 , further including a synchronization control circuit, establishing an instant of startup of the series of control signals in relation to the global operation of the pixel matrix, and notably in relation to the readout rate for the rows of the matrix.
3. The image sensor according to claim 1 , wherein the memory includes several areas, each area corresponding to a respective group of control signals to be established, and the sequencing circuit comprises a programmable register into which there are written an item of information indicating the start of the memory area to be used and an item of information indicating the number of successive addresses to be used for this area.
4. The image sensor according to claim 1 , wherein the memory controller comprises two operating modes which are respectively a utilization mode, to establish the control signals when the sensor is operating, and a programming mode to write into the memory the binary words corresponding to the control signals to be established.
5. The image sensor according to claim 4 , including a programming interface circuit for establishing a communication between a processor external to the sensor and the memory controller in order to perform the desired programming from outside the sensor.
6. The image sensor according to claim 5 , further including a synchronization control circuit, establishing an instant of startup of the series of control signals in relation to the global operation of the pixel matrix, and notably in relation to the readout rate for the rows of the matrix.
7. The image sensor according to claim 5 , wherein the memory includes several areas, each area corresponding to a respective group of control signals to be established, and the sequencing circuit comprises a programmable register into which there are written an item of information indicating the start of the memory area to be used and an item of information indicating the number of successive addresses to be used for this area.