Image sensor with buried-channel drain (BCD) transistors
A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include a load transistor implemented using a buried-channel drain (BCD) structure. The load transistor may include a gate conductor, a source diffusion region, a drain diffusion region, and a buried-channel drain region that at least partially extends under the gate conductor. The BCD region may be formed before or after the formation of the gate conductor. If desired, the BCD region can also be formed at the source edge. An image sensor configured in this way can exhibit higher source-drain breakdown voltages, enhanced amplifier gain, and reduced amplifier glow.
1. An image sensor, comprising:
photosensitive elements that generate charge; and
an output buffer circuit that receives the charge from the photosensitive elements and that includes a load transistor, wherein the load transistor includes a gate conductor and a buried-channel drain region that extends partially beneath only a portion of the gate conductor.
2. The image sensor of claim 1 , wherein the output buffer circuit includes a source-follow transistor coupled in series with the load transistor, and wherein the gate conductor of the load transistor receives a fixed bias voltage signal.
3. The image sensor of claim 1 , wherein the gate conductor overlaps with at least a portion of the buried-channel drain region.
4. The image sensor of claim 1 , wherein the buried-channel drain region has a first portion that is covered by the gate conductor and a second portion that is not covered by the gate conductor.
5. The image sensor of claim 4 , wherein the first and second portions of the buried-channel region have different lengths.
6. The image sensor of claim 4 , wherein the first and second portions of the buried-channel region have identical lengths.
7. The image sensor of claim 4 , wherein the first and second portions of the buried-channel region have different dopant concentrations.
8. The image sensor of claim 4 , wherein the first and second portions of the buried-channel region have identical dopant profiles.
9. The image sensor of claim 1 , wherein the load transistor has a symmetrical source and drain transistor structure.
10. The image sensor of claim 1 , wherein the load transistor has an asymmetric source and drain transistor structure.