Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins

1. A method for forming a finFET device, comprising:

forming an n-doped region and a p-doped region in a semiconductor wafer;

forming a layer of silicon above both the n-doped and p-doped regions;

removing a portion of the silicon layer above the n-doped region to form a first recess;

implanting n-type dopants into the first recess after forming the first recess;

forming a layer of silicon germanium in the first recess after implanting the n-type dopants into the first recess;

etching away at least a portion of the silicon layer and the underlying p-doped region;

etching away at least a portion of the silicon germanium layer and the underlying n-doped region;

forming fins of the finFET device from the unetched silicon and silicon germanium layers; and

forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.

2. The method of claim 1 , further comprising forming a silicon carbon layer intermediate the layer of silicon and the n-doped and p-doped regions.

3. The method of claim 2 , wherein forming the layer of silicon carbon intermediate the layer of silicon and the n-doped and p-doped regions further comprises forming a layer of silicon carbon having a carbon concentration in a range of 0.05% to 1% and a thickness in a range of 2 nm to 50 nm.

4. The method of claim 2 , wherein forming the layer of silicon carbon intermediate the layer of silicon and the n-doped and p-doped regions further comprises forming a layer of silicon carbon having a carbon concentration in the range of 0.1% to 0.4% and a thickness in a range of 5 nm to 20 nm.

5. The method of claim 2 , wherein removing the portion of the silicon layer above the n-doped region to create the first recess further comprises etching the silicon layer until the etching process reaches the silicon carbon layer.

6. The method of claim 1 , wherein removing the portion of the silicon layer above the n-doped region to create the first recess further comprises etching the silicon layer until the etching process reaches the n-doped region.

7. The method of claim 1 , wherein forming the p-doped region in the semiconductor wafer further comprises forming the p-doped region in the semiconductor wafer by patterned ion implantation of at least one p-type dopant from the group of boron (B), gallium (Ga), and indium (In) using a peak dopant concentration in a range of 1e18 atoms/cm 3 to 2e19 atoms/cm 3 .

8. The method of claim 1 , wherein forming the n-doped region in the semiconductor wafer further comprises forming the n-doped region in the semiconductor wafer by patterned ion implantation of at least one n-type dopant from the group of phosphorus (P), arsenic (As), and antimony (Sb) using a peak dopant concentration in a range 1e18 atoms/cm 3 to 2e19 atoms/cm 3 .

9. The method of claim 1 , wherein forming a layer of silicon above the n-doped and p-doped regions further comprises forming an epitaxial silicon layer having a thickness in a range of 30 nm to 80 nm.

10. The method of claim 1 , wherein forming a silicon germanium layer further comprises forming an epitaxial silicon germanium layer grown selectively on exposed crystalline silicon regions and having a germanium concentration in a range of 20% to 50% and having a thickness in a range of 30 nm to 80 nm.

11. The method of claim 1 , wherein etching away at least a portion of the silicon layer and the underlying p-doped region, and etching away at least a portion of the silicon germanium layer and the underlying n-doped region further comprises using a single etching process to etch away at least a portion of the silicon layer and the underlying p-doped region and etching away at least a portion of the silicon germanium layer and the underlying n-doped region.