Fin field effect transistor and method for fabricating the same
A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.
1. A fin field effect transistor (FinFET), comprising:
a substrate having a semiconductor fin;
a gate stack disposed across the semiconductor fin;
lightly doped source and drain (LDD) regions beside the gate stack; and
strained source and drain regions located within recesses of the semiconductor fin beside the gate stack, wherein at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion,
wherein the top portion has a body and a region, the body is located on the bottom portion, and the region is connected with the body, extends beyond a sidewall of the bottom portion and toward a channel region under the gate stack,
wherein at least one of the LDD regions is under the region and beside the bottom portion.
2. The FinFET of claim 1 , wherein the region has a rectangle profile.
3. The FinFET of claim 1 , wherein a top corner and a bottom corner of the region are rounded.
4. The FinFET of claim 1 , wherein a width of the region is in a range from about 2 nm to about 6 nm.
5. The FinFET of claim 1 , wherein a depth of the region is in a range from about 2 nm to about 6 nm.
6. The FinFET of claim 1 , wherein the bottom portion has a hemispherical profile, a semi-elliptical profile, or a bulb-like profile.
7. The FinFET of claim 1 , wherein the at least one of the strained source and drain regions has a rotated p-shape profile, a rotated b-shape profile, a σ profile, a reversed Ω profile.
8. The FinFET of claim 1 , wherein a depth of the top portion is smaller than a depth of the bottom portion.
9. The FinFET of claim 1 , further comprising spacers located on sidewalls of the gate stack, wherein the region is covered by one of the spacers.
10. The FinFET of claim 1 , wherein a doping concentration of the top portion is higher than a doping concentration of the at least one of the LDD regions.
11. A fin field effect transistor (FinFET), comprising:
a substrate having a semiconductor fin;
a gate stack disposed across the semiconductor fin;
spacers located on sidewalls of the gate stack; and
strained source and drain located within recesses of the semiconductor fin beside the gate stack, wherein at least one of the strained source and drain has a region below the spacers and toward a channel region under the gate stack, and has at least one notch below the region, and the at least one notch is separated from the spacers by the region.
12. The FinFET of claim 11 , wherein the at least one notch has a V-shape.
13. The FinFET of claim 11 , further comprising lightly doped source and drain (LDD) regions beside the gate stack, wherein at least one of the LDD regions covers the notch.
14. The FinFET of claim 13 , wherein a doping concentration of the at least one of the strained source and drain is higher than a doping concentration of the at least one of the LDD regions.
15. The FinFET of claim 11 , wherein the semiconductor fin between the strained source and drain has a multi-step structure.
16. A method for fabricating a fin field effect transistor (FinFET), comprising:
providing a substrate having a semiconductor fin;
forming a gate stack across the semiconductor fin;
forming a first spacer material layer over the substrate;
performing a plasma doping process and a thermal anneal process so as to form lightly doped source and drain (LDD) regions in the semiconductor fin beside the gate stack, wherein a doping concentration of top regions of the LDD regions is higher than a doping concentration of bottom regions of the LDD regions;
forming a second spacer material layer over the first spacer material layer;
performing a first etching process to form trenches in the semiconductor fin beside the gate stack;
performing a second etching process to locally push the top regions of the LDD regions, so as to form recesses having notches in profiles; and
forming strained source and drain regions to fill in the recesses.
17. The method of claim 16 ,
wherein the step of performing the plasma doping process comprises:
forming a dopant layer on the first spacer material layer and forming a doped region in the semiconductor fin;
performing a knock-in process so that dopants of the dopant layer are knocked into the first spacer material layer; and
removing the dopant layer, and
wherein the thermal anneal process is performed to drive the dopants in the first spacer material layer into the doped regions, so as to form the LDD regions.
18. The method of claim 17 , wherein the second etching process comprises an isotropic etching process, and an etching rate of the top regions of the LDD regions is higher than an etching rate of the bottom portions of the LDD regions during the isotropic etching process.