Silicon phosphide semiconductor device
A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH 3 ) and at least one of arsine (AsH 3 ) or monomethylsilane (CH 6 Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.
1. A semiconductor device comprising:
a first source/drain region in a first semiconductor fin, the first source/drain region comprising a first single continuous material extending from a bottom surface of the first source/drain region to above a top surface of the first semiconductor fin, the first single continuous material comprising SiP:C:As;
a gate over and along sidewalls of the first semiconductor fin;
a gate seal spacer on a sidewall of the gate; and
a gate spacer on a sidewall of the gate seal spacer, wherein the first source/drain region contacts a vertical sidewall of the gate seal spacer, and a top surface of the gate seal spacer, and a sidewall of the gate spacer.
2. The semiconductor device of claim 1 , wherein the first source/drain region contacts the vertical sidewall of the gate seal spacer in a first cross-sectional view, and wherein the first source/drain region contacts the sidewall of the gate spacer in a second cross-sectional view different from the first cross-sectional view.
3. The semiconductor device of claim 1 , wherein the first source/drain region extends directly below the gate spacer.
4. The semiconductor device of claim 1 , further comprising a second source/drain region in a second semiconductor fin, the second source/drain region comprising a second single continuous material having a same material composition as the first single continuous material, the second single continuous material directly contacting the first single continuous material of the first source/drain region.
5. The semiconductor device of claim 4 , further comprising a shallow trench isolation (STI) region between the first semiconductor fin and the second semiconductor fin, wherein the first source/drain region contacts a vertical sidewall of the STI region.
6. The semiconductor device of claim 1 , wherein the bottom surface of the first source/drain region is disposed a distance from 35 to 60 nm below the top surface of the first semiconductor fin, and wherein the first source/drain region has a width from 20 to 35 nm.
7. The semiconductor device of claim 1 , wherein the first single continuous material has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 and a carbon concentration from 0.1 to 2 atomic percent.
8. The semiconductor device of claim 1 , wherein the first single continuous material has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 and an arsenic concentration from 1×10 20 to 3×10 21 atoms/cm 3 .
9. The semiconductor device of claim 1 , further comprising:
a silicide region in the first single continuous material in the first source/drain region; and
a source/drain contact extending into the silicide region to be electrically connected to the first source/drain region.
10. The semiconductor device of claim 9 , wherein the silicide region has a thickness of 2 to 10 nm.
11. A semiconductor device comprising:
a fin extending from a substrate;
a gate stack over the fin;
a gate seal spacer extending along a sidewall of the gate stack;
a gate spacer extending along a sidewall of the gate seal spacer;
an epitaxial source/drain region in the fin adjacent the gate spacer, wherein the epitaxial source/drain region comprises a first material made of SiP doped with arsenic, wherein the first material directly contacts a horizontal surface of the fin, a vertical surface of the fin, a vertical surface of the gate seal spacer, and the gate spacer, wherein a first width of the epitaxial source/drain region in a direction parallel to a major surface of the substrate at a point level with a top surface of the fin is less than a second width of the epitaxial source/drain region in the direction parallel to the major surface of the substrate at a point below the top surface of the fin; and
a silicide region in the first material of the epitaxial source/drain region.
12. The semiconductor device of claim 11 , wherein the first material further comprises carbon.
13. The semiconductor device of claim 11 further comprising a source/drain contact extending into the silicide region to be electrically coupled to the epitaxial source/drain region.
14. The semiconductor device of claim 11 further comprising an isolation region around the fin, wherein the first material of the epitaxial source/drain region directly contacts a vertical surface of the isolation region.
15. The semiconductor device of claim 11 further comprising a lightly doped source/drain (LDD) region in the fin, wherein the first material of the epitaxial source/drain region directly contacts the LDD region.
16. A method comprising:
etching a first semiconductor fin to form a first recess;
etching a second semiconductor fin to form a second recess;
epitaxially growing a first semiconductor material in the first recess and a second semiconductor material in the second recess until the first semiconductor material merges with the second semiconductor material, the first semiconductor material extending from a bottom surface of the first recess to above a top surface of the first semiconductor fin, the second semiconductor material extending from a bottom surface of the second recess to above a top surface of the second semiconductor fin, the first semiconductor material and the second semiconductor material each comprising SiP:C:As; and
forming a gate over the first semiconductor fin and the second semiconductor fin adjacent the first semiconductor material and the second semiconductor material.
17. The method of claim 16 , further comprising:
forming a gate seal spacer on a sidewall of the gate; and
forming a gate spacer on a sidewall of the gate seal spacer, wherein the first semiconductor material contacts a sidewall of the gate seal spacer, a top surface of the gate seal spacer, and a sidewall of the gate spacer.
18. The method of claim 16 , wherein epitaxially growing the first semiconductor material and the second semiconductor material comprises flowing phosphine as a first precursor.
19. The method of claim 18 , wherein epitaxially growing the first semiconductor material and the second semiconductor material comprises flowing arsine (AsH 3 ) or monomethylsilane (CH 6 Si) as a second precursor.
20. The method of claim 16 , wherein maximum width of the first semiconductor material above the top surface of the first semiconductor fin is less than a maximum width of the first semiconductor material below the top surface of the first semiconductor fin in a cross-sectional view.