Forming enhancement mode III-nitride devices
A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.
1. A III-N device, comprising:
a III-N material structure comprising a III-N channel layer and a III-N barrier layer;
a source contact and a drain contact electrically coupled to the channel layer;
an insulator layer on the III-N material structure;
a gate insulator at least partially in a first trench, the first trench extending through the insulator layer and into the III-N material structure, a portion of the trench that extends into the III-N material structure having first sidewalls that are substantially more vertical than second sidewalls of the portion of the trench that is through the insulator layer, the gate insulator being on a top surface of the channel layer; and
a first gate electrode deposited conformally on top of the gate insulator and at least partially in the first trench, the first gate electrode being positioned between the source and drain contacts;
a second trench between the first gate electrode and the drain contact; and
a second gate electrode at least partially in the second trench.
2. The III-N device of claim 1 , wherein the first sidewalls of the trench are vertical and the second sidewalls of the trench are slanted.
3. The III-N device of claim 1 , wherein the gate electrode includes extending portions that are outside the trench and extend towards but are separated from the source and drain contacts, respectively.
4. The III-N device of claim 1 , wherein the barrier layer has a larger bandgap than the channel layer, such that a conductive channel is induced in the channel layer.
5. The III-N device of claim 4 , wherein the source and drain contacts form respective ohmic contacts that are electrically coupled to the conductive channel.
6. The III-N device of claim 5 , wherein the conductive channel is discontinuous in a region of the channel layer beneath the trench when 0V is applied to the gate electrode relative to the source contact, but is continuous when a voltage greater a threshold voltage of the device is applied to the gate electrode relative to the source contact, the threshold voltage being greater than 0V.
7. The III-N device of claim 6 , wherein the III-N device functions as an enhancement-mode field effect transistor, the threshold voltage of the transistor is more than 2 V, and a threshold voltage hysteresis of the transistor is less than 0.5 V.
8. The III-N device of claim 1 , wherein the gate insulator is an amorphous film comprising N and at least one of Al and Si.
9. The III-N device of claim 8 , wherein a thickness of the amorphous film is between 1 nm and 60 nm.
10. The III-N device of claim 1 , wherein the III-N channel layer includes a III-N layer without Aluminum (Al) and the III-N barrier layer includes an Al-based III-N layer.
11. The III-N device of claim 1 , wherein the gate insulator is an amorphous film comprising Al and Si.
12. The III-N device of claim 11 , wherein a ratio of the silicon fractional composition to the aluminum fractional composition in the amorphous film is less than ⅓.