Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
1. An integrated circuit wafer comprising:
(a) a first die having:
i. die pads;
ii. core circuitry coupled to the die pads;
iii. a scan path in the core circuitry, the scan path having a scan path input coupled to a first die pad and a scan path output;
iv. a test circuit having a scan path input coupled to the scan path output, an expected data input coupled to a second die pad, a mask data input coupled to a third die pad, a first serial scan path input, and a first serial scan path output;
(b) a second die having:
i. die pads;
ii. core circuitry coupled to the die pads;
iii. a scan path in the core circuitry, the scan path having a scan path input coupled to a first die pad and a scan path output;
iv. a test circuit having a scan path input coupled to the scan path output, an expected data input coupled to a second die pad, a mask data input coupled to a third die pad, a second serial scan path input, and a second serial scan path output; and
(c) first leads coupling the first die pads together, second leads coupling the second die pads together, and third leads coupling the third die pads together.
2. The integrated circuit wafer of claim 1 in which the first serial scan path output is coupled to the second serial scan path input.
3. The integrated circuit wafer of claim 1 including tester circuitry having leads coupled to the die pads of the first and second die.