Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.
1. An apparatus, comprising:
a block of memory including a first sub-block and a second sub-block, the first sub-block and the second sub-block including a first plurality of memory cell strings and a second plurality of memory cell strings, respectively, coupled to a common data line, the block of memory further including
a first segmented source coupled to the first plurality of memory cell strings, and
a second segmented source coupled to the second plurality of memory cell strings, the first segmented source and the second segmented source being electrically isolated from each other.
2. The apparatus of claim 1 , wherein the first sub-block and the second sub-block each share a common source select line.
3. The apparatus of claim 1 , further comprising drain select devices coupled to each of the first plurality of memory cell strings and the second plurality of memory cell strings, the drain select devices having an asymmetric dopant profile.
4. The apparatus of claim 3 , wherein the drain select devices within the first sub-block are electrically isolated from the drain select devices in the second sub-block.
5. The apparatus of claim 1 , wherein the first sub-block and the second sub-block of the block of memory share a plurality of common access lines.
6. The apparatus of claim 1 , further comprising a drain select device on a data line side and a source select device on a source side coupled to each of the first plurality of memory cell strings and each of the second plurality of memory cell strings, an SGD junction on the data line side having a junction breakdown-voltage that is asymmetric with reference to an SGS junction on the source side.
7. The apparatus of claim 1 , wherein the apparatus is configured to apply a first bias voltage to one of the first segmented source and the second segmented source of a sub-block selected to be erased during an erase operation, and apply a second bias voltage to the other segmented source of a sub-block of the block of memory not selected to be erased during the erase operation, the first bias voltage being greater than the second bias voltage.
8. The apparatus of claim 1 , wherein the first sub-block and the second sub-block of the block of memory do not share a memory cell.
9. An apparatus, comprising:
a block of memory including a first sub-block and a second sub-block, the first sub-block and the second sub-block including a first plurality of memory cell strings and a second plurality of memory cell strings, respectively, the first plurality of memory cell strings and the second plurality of memory cell strings being coupled to a common data line through a plurality of drain select devices, the block of memory further comprising
a first segmented source coupled to the first plurality of memory cell strings in the first sub-block through a first plurality of source select devices, and
a second segmented source coupled to the second plurality of memory cell strings in the second sub-block through a second plurality of source select devices.
10. The apparatus of claim 9 , wherein the first plurality of source select devices and the second plurality of source select devices each have a higher breakdown voltage than each of the plurality of drain select devices.
11. The apparatus of claim 9 , wherein the first plurality of memory cell strings and the second plurality of memory cell strings, in the first sub-block and the second sub-block, respectively, are each independently erasable from one another.
12. The apparatus of claim 9 , wherein each of the drain select devices has an asymmetric dopant profile.
13. The apparatus of claim 12 , wherein the asymmetric dopant profile in the drain select devices is configured to prevent a reverse bias condition in a channel of memory cell strings in one of the sub-blocks that is not selected for an erase operation.
14. An apparatus, comprising:
a block of memory having two or more segmented portions, each of the two or more segmented portions forming separate sub-blocks of the block of memory;
a plurality of memory cells in each of the sub-blocks in the block of memory, the plurality of memory cells being coupled by a common data line, the plurality of memory cells within one sub-block configured to be erasable independently of memory cells in another sub-block; and
a plurality of segmented sources, distinct ones of the plurality of segmented sources each coupled separately to one of the sub-blocks of memory, each of the plurality of segmented sources being electrically isolated from remaining ones of the plurality of segmented sources.
15. The apparatus of claim 14 , wherein each of the plurality of segmented sources is configured to receive a bias level independent of bias levels received by remaining ones of the plurality of segmented sources.
16. The apparatus of claim 14 , wherein each of the plurality of memory cells in each of the sub-blocks further includes a source select devices.
17. The apparatus of claim 16 , wherein the source select devices in each of the sub-blocks are electrically coupled to one another.
18. The apparatus of claim 14 , wherein the sub-blocks are each comprised of non-overlapping portions of the plurality of memory cells.
19. A three-dimensional device, comprising:
a first sub-block and a second sub-block including a first plurality of memory strings and a second plurality of memory strings, respectively, each of the plurality of memory strings including a plurality of memory cells and coupled to a segmented source line, the segmented source line of the first plurality of memory strings and the segmented source line of the second plurality of memory strings being electrically isolated from each other; and
a common data line coupled to the first plurality of memory strings and the second plurality of memory strings.
20. The three-dimensional device of claim 19 , wherein the first sub-block and the second sub-block further comprise at least one of segmented access lines and segmented source select lines.
21. The three-dimensional device of claim 20 , wherein each of the segmented access lines and the segmented source select lines within the first sub-block are electrically isolated from the segmented access lines and the segmented source select lines within the second sub-block.
22. The three-dimensional device of claim 19 , further comprising:
a first segmented source coupled to the first sub-block; and
a second segmented source coupled to the second sub-block.
23. The three-dimensional device of claim 22 , wherein the device is configured to apply a bias voltage to the segmented source of a selected one of the sub-blocks that is higher than a bias voltage applied to the segmented source of the non-selected one of the sub-blocks.
24. The three-dimensional device of claim 19 , the memory block having common access lines and a common data line coupled to at least the first plurality of memory strings and the second plurality of memory strings.
25. The three-dimensional device of claim 19 , wherein the memory block is configured to allow a selected one of the first sub-block and the second sub-block to be erased separately from a non-selected sub-block by a selection of bias voltages applied to segmented drain select lines and segmented source lines within each of the sub-blocks.
26. The three-dimensional device of claim 25 , wherein the segmented source line of the selected one of the sub-blocks is configured to have a higher bias voltage applied than a bias voltage applied to the segmented source line of the non-selected one of the sub-blocks.