IP Library Granted Patent US 9,666,475
Granted Patent B2
US 9,666,475 · App. 15/083,793 · Granted May 30, 2017

Semiconductor structure with airgap

Inventors: Mark D. Jaffe (Shelburn, VT); Alvin J. Joseph (Williston, VT); Qizhi Liu (Lexington, MA); Anthony K. Stamper (Burlington, VT)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L21/764H01L21/0273H01L21/02233H01L21/02238H01L21/266H01L21/26533H01L21/30604H01L21/76224H01L21/76283H01L29/0649H01L29/0653H01L29/66651H01L29/78H01L21/02255
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Quick Facts
Patent No.
US 9,666,475
App. No.
15/083,793
Granted
May 30, 2017
Kind
B2
Abstract

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Claims (20)

1. A method, comprising:

forming an amorphous layer under an active region of a substrate;

forming an airgap in the substrate under the amorphous layer; and

forming an isolated transistor in the active region, above the amorphous layer and the airgap.

2. The method of claim 1 , wherein the isolated transistor is surrounded by shallow trench isolation regions.

3. The method of claim 2 , wherein the transistor is formed as a completely isolated transistor.

4. The method of claim 1 , wherein amorphous layer is formed by an ion implantation process, prior to the formation of the transistor.

5. The method of claim 1 , wherein the formation of the amorphous layer comprises:

forming a resist on the substrate;

patterning the resist to form an opening over the active region; and

performing the ion implantation process through the opening, prior to the formation of the transistor and airgap.

6. The method of claim 5 , wherein the formation of the airgap comprises:

etching the substrate with NH 4 OH to form a trench and an undercut extending laterally below the active region; and

filling the trench with a material,

wherein the amorphous layer is an etch stop layer for the etching of the substrate.

7. The method of claim 6 , wherein the material is poly material deposited within the trench.

8. The method of claim 1 , further comprising forming another amorphous layer on a bottom surface of the airgap.

9. The method of claim 1 , further comprising forming a perimeter of amorphous material surrounding the active region of the transistor.

10. The method of claim 1 , wherein the ion implantation process comprises ion implanting species of Ge or Ar.

11. The method of claim 1 , further comprising oxidizing a bottom surface of a lateral undercut to form an amorphous layer on a bottom surface of the airgap opposing the amorphous material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: JAFFE, MARK D.; JOSEPH, ALVIN J.; LIU, QIZHI; STAMPER, ANTHONY K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038127/0378 →
Continuity (2)
Continuation 14480215 · Sep 8, 2014
Related Publication 20160211167A1 · Jul 21, 2016