Apparatuses and related methods for staggering power-up of a stack of semiconductor dies

1. An apparatus, comprising:

a first semiconductor die including at least one first power input and a first voltage monitor; and

a second semiconductor die including at least one second power input and a second voltage monitor, wherein:

the first semiconductor die and the second semiconductor die form a stack;

the first voltage monitor is configured to generate a first power-up ok signal responsive to a power-up event detected based on a power supply voltage;

the first semiconductor die is configured to power up at a first time responsive to a first power-up go signal generated when both the first power-up ok signal and the at least one first power input are asserted;

the first semiconductor die is further configured to output a first output signal to the at least one second power input of the second semiconductor die responsive to the first die completing power up;

the second voltage monitor is configured to generate a second power-up ok signal responsive to the power-up event based on the power supply voltage;

the second semiconductor die is configured to power up at a second time responsive to a second power-up go signal generated when both the second power-up ok signal and the at least one second power input are asserted,

wherein the first voltage monitor is configured to:

detect the power-up event by monitoring a power supply voltage and detecting the power supply voltage to have a magnitude above a predetermined threshold; and

generate a reset signal responsive to detecting the magnitude of the power supply voltage to drop below a predetermined reset threshold, and wherein the first semiconductor die is configured to power down responsive to the reset signal.

2. The apparatus of claim 1 , wherein a second input signal is the first output signal from the first semiconductor die.

3. The apparatus of claim 1 , further comprising a memory device including the stack including the first semiconductor die and the second semiconductor die.

4. The apparatus of claim 3 , wherein the memory device is a virtual chip enable memory device.

5. The apparatus of claim 3 , further comprising:

a processor;

an input device; and

an output device, wherein the processor is operably coupled to the memory device, the input device, and the output device.

6. The apparatus of claim 1 , wherein the second voltage monitor is configured to detect the power-up event by monitoring a power supply voltage and detecting the power supply voltage to have a magnitude above a predetermined threshold.

7. The apparatus of claim 1 wherein the predetermined reset threshold is approximately a minimum operational voltage of the first semiconductor die.

8. An apparatus comprising:

a first semiconductor die including at least one first power input; and

a second semiconductor die including at least a second power input operably coupled to the at least one first power input, wherein the first semiconductor die and the second semiconductor die form a stack, wherein, responsive to a power-up event, the first semiconductor die is configured to power up at a first time, and the second semiconductor die is configured to power up at a second time that is different from the first time,

wherein:

the first semiconductor die is configured to power up responsive to the power-up event;

the first semiconductor die is further configured to output a first output signal to the second semiconductor die responsive to the first die completing power up;

the second semiconductor die is configured to power up responsive to receiving the first output signal from the first semiconductor die;

the first semiconductor die includes a first voltage monitor configured to generate a first power-up ok signal responsive to the power-up event, wherein the first semiconductor die is configured to power up when both the first power-up ok signal and a first input signal are asserted;

the second semiconductor die includes a second voltage monitor configured to generate a second power-up ok signal responsive to the power-up event, wherein the second semiconductor die is configured to power up when both the second power-up ok signal and a second input signal are asserted;

the first semiconductor die further includes a first AND gate operably coupled with the first voltage monitor, the first AND gate configured to generate a first power-up go signal to initiate power up of the first semiconductor die when both the first power-up ok signal and a first input signal are asserted; and

the second semiconductor die further includes a second AND gate operably coupled with the second voltage monitor, the second AND gate configured to generate a second power-up go signal to initiate power up of the second semiconductor die when both the second power-up ok signal and a second input signal are asserted.

9. A method of powering up an electronic device, the method comprising:

detecting a power-up event with a plurality of semiconductor dies in a stack of semiconductor dies within a common package;

generating a power-up ok signal responsive to detecting the power-up event;

powering up a first semiconductor die of the stack of semiconductor dies at a first time responsive to the power-up ok signal being asserted;

powering up a second semiconductor die of the stack of semiconductor dies at a second time that is different from the first time responsive to receiving a first output signal from the first semiconductor die indicating that the first semiconductor die has finished powering up, and responsive to both the power-up ok signal and the first output signal from the first semiconductor die being asserted; and

receiving, at an AND gate for the second semiconductor die, the power-up ok signal and the first output signal to generate a power-up go signal to initiate power up of the second semiconductor die.

10. The method of claim 9 , wherein generating the power-up ok signal is responsive to a first voltage monitor of the first semiconductor die detecting the power-up event, the method further comprising the second semiconductor die generating another power-up ok signal responsive to a second voltage monitor of the second semiconductor die detecting the power-up event.

11. The method of claim 10 , wherein:

generating the power-up ok signal for the first semiconductor die is responsive to the first voltage monitor detecting the power-up event by detecting a magnitude of the power supply voltage at the first semiconductor die being above a predetermined threshold; and

generating another power-up ok signal as the power-up ok signal for the second semiconductor die is responsive to detecting the power-up event by detecting the magnitude of the power supply voltage at the second semiconductor die being above the predetermined threshold.

12. The method of claim 9 , further comprising:

generating a reset signal responsive to detecting a lack of the power-up event; and

powering down the first semiconductor die and the second semiconductor die responsive to the reset signal.

13. The method of claim 12 , wherein generating a reset signal responsive to detecting a lack of the power-up event includes detecting the magnitude of a power supply signal voltage dropping below a predetermined reset threshold voltage.

14. An apparatus of comprising:

a first semiconductor die including at least one first power input and a first voltage monitor;

a second semiconductor die including at least one second power input and a second voltage monitor, wherein:

the first semiconductor die and the second semiconductor die form a stack;

the first voltage monitor is configured to generate a first power-up ok signal responsive to a power-up event detected based on a power supply voltage;

the first semiconductor die is configured to power up at a first time responsive to a first power-up go signal generated when both the first power-up ok signal and the at least one first power input are asserted;

the first semiconductor die is further configured to output a first output signal to the at least one second power input of the second semiconductor die responsive to the first die completing power up;

the second voltage monitor is configured to generate a second power-up ok signal responsive to the power-up event based on the power supply voltage;

the second semiconductor die is configured to power up at a second time responsive to a second power-up go signal generated when both the second power-up ok signal and the at least one second power input are asserted; and

a first AND gate configured to receive the first power-up ok signal and the at least one first power input and output the first power-up go signal; and

a second AND gate configured to receive the second power-up ok signal and the at least one second power input and output the second power-up go signal.