Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
1. A method comprising:
packaging a memory device, the memory device comprising a memory array, non-volatile memory and volatile memory, wherein the non-volatile memory and the volatile memory are configured to store defective address data; and
entering, after the memory device has been packaged, into a soft post package repair mode to perform:
receiving first defective address data, the first defective address data corresponding to an address of the memory array to be accessed that includes at least one defective memory cell; and
storing and holding the first defective address data into the volatile memory without being loaded to the non-volatile memory.
2. The method of claim 1 , further comprising entering, after exiting the soft post package repair mode, into a data access mode to perform:
receiving address data, the address data corresponding to an address of the memory array to be accessed; and
asserting a first match signal if the address data matches the first defective address data that is stored and held into the volatile memory.
3. The method of claim 2 , wherein the memory device further comprises a redundant memory, and wherein the method further comprises accessing the redundant memory responsive, at least in part, to the first match signal.
4. The method of claim 3 , wherein the redundant memory is included in the memory array.
5. The method of claim 1 , further comprising storing and holding, before the memory device is packaged, second defective address data into the non-volatile memory, the second defective address data corresponding to another address of the memory array to be accessed that includes at least one defective memory cell.
6. The method of claim 5 , further comprising entering, after exiting the soft post package repair mode, into a data access mode to perform:
receiving address data, the address data corresponding to an address of the memory array to be accessed; and
asserting a first match signal if the address data matches the first defective address data that is stored and held into the volatile memory or a second match signal if the address data matches the second defective address data that is stored and held into the non-volatile memory.
7. The method of claim 6 , wherein the memory device further comprises a first redundant memory and the second redundant memory, and wherein the method further comprises accessing the first redundant memory responsive, at least in part, to the first match signal or the second redundant memory responsive, at least in part, to the second match signal.
8. The method of claim 7 , wherein each of the first redundant memory and the second redundant memory is included in the memory array.
9. A method comprising:
detecting, before packaging a memory device that comprises a memory array, non-volatile memory and volatile memory, first defective address data corresponding to a first address of the memory array to be accessed that includes at least one defective memory cell;
storing and holding, before packaging the memory device, the first defective address data into the non-volatile memory;
packaging the memory device;
detecting, after packaging the memory device, second defective address data corresponding to a second address of the memory array to be accessed that includes at least one defective memory cell;
storing and holding, after packaging the memory device, the second defective address data into the volatile memory without being loaded to the non-volatile memory; and
performing a data access operation on the memory device while the second detective address data is being stored and held into the volatile memory.
10. The method of claim 9 , wherein the performing the data access operation comprises:
receiving address data to be accessed; and
asserting a first match signal if the address data matches the first defective address data that is stored and held into the non-volatile memory or a second match signal if the address data matches the second defective address data that is stored and held into the volatile memory.
11. The method of claim 10 , wherein the memory device further comprises first and second redundant memories, and wherein the performing the data access operation further comprises accessing the first redundant memory if the first match signal is asserted or the second redundant memory if the second match signal is asserted.
12. The method of claim 11 , wherein each of the first and second redundant memories is included in the memory array.
13. The method of claim 9 , wherein at least the storing and holding the second defective address data is included in a soft post package repair mode and each of the detecting the first defective address data and the storing and holding the first defective address data is excluded from the soft post package repair mode.
14. The method of claim 12 , wherein the second address of the memory array corresponds with an address of the first redundant memory.
15. A memory device comprising:
a memory array;
a volatile memory configured to store first defective address data, the first defective address data corresponding to a first address of the memory array that includes at least one defective memory cell;
a non-volatile memory configured to store second defective address data, the second defective address data corresponding to a second address of the memory array that includes at least one defective memory cell;
a set of address terminals configured to be supplied with address data to be accessed;
a first logic circuit configured to assert a first match signal when the address data to be accessed matches the first defective address data that is stored and held into the volatile memory; and
a second logic circuit configured to assert a second match signal when the address data to be accessed matches the second defective address data that is stored and held into the non-volatile memory.
16. The memory device of claim 15 , wherein the memory device further comprises a first redundant memory and a second redundant memory, wherein the first logic circuit causes the first redundant memory to be accessed by assertion of the first match signal, and wherein the second logic circuit causes the second redundant memory to be accessed by assertion of the second match signal.
17. The memory device of claim 16 , wherein the second redundant memory is included in the memory array.
18. The memory device of claim 17 , each of cells included in the memory array comprises a DRAM cell.
19. The memory device of claim 17 , wherein the first redundant memory is included in the memory array.
20. The memory device of claim 19 , each of cells included in the memory array comprises a DRAM cell.