S/D contact resistance measurement on FinFETs

1. A contact resistance test device, comprising:

a set of full fins providing channels between a source region and a drain region;

a set of partial fins connected to the source region and electrically isolated from the drain region;

a gate structure formed over the set of full fins and set of partial fins;

a source contact connected to the source region; and

a probe contact isolated from the source contact and connected to the source region wherein a voltage measured between the probe contact and the source contact measures contact resistance when a drain-to-source current is flowing in the set of full fins.

2. The device as recited in claim 1 , wherein the probe contact includes an equal potential with the source region.

3. The device as recited in claim 1 , wherein the source region includes an epitaxially grown region etched to provide an interface with the source contact and the probe contact.

4. The device as recited in claim 3 , wherein the source contact and the probe contact connect to the epitaxially grown region over the set of full fins and the set of partial fins.

5. The device as recited in claim 1 , further comprising a shallow trench isolation region formed at a base of the set of full fins and the set of partial fins.

6. The device as recited in claim 1 , wherein a conductor of the gate structure is formed over free edges of the set of partial fins.

7. The device as recited in claim 1 , wherein the source region includes a continuous epitaxial region connecting the set of full fins and the set of partial fins.

8. A contact resistance test device, comprising:

a semiconductor substrate;

a set of full fins etched into the substrate;

a set of partial fins etched from the set of full fins;

a source region epitaxially grown on first end portions of the set of full fins and the set of partial fins;

a drain region epitaxially grown on second end portions of the set of full fins, the full fins forming channels between the source region and the drain region, and the drain region being electrically isolated from the partial fins;

a gate structure formed over the set of full fins and the set of partial fins;

a source contact connected to the source region corresponding to the set of full fins; and

a probe contact connected to the source region corresponding to the set of partial fins, the probe contact being isolated from the source contact wherein a voltage measured between the probe contact and the source contact measures contact resistance when a drain-to-source current is flowing in the set of full fins.

9. The device as recited in claim 8 , wherein the probe contact includes an equal potential with the source region.

10. The device as recited in claim 9 , wherein the source region includes etched surfaces to provide an interface with the source contact and the probe contact.

11. The device as recited in claim 10 , wherein the source contact and the probe contact connect to the source region over the set of full fins and the set of partial fins, respectively.

12. The device as recited in claim 9 , further comprising a shallow trench isolation region formed at a base of the set of full fins and the set of partial fins.

13. The device as recited in claim 9 , wherein a conductor of the gate structure is formed over free edges of the set of partial fins.

14. The device as recited in claim 9 , wherein the source region includes a continuous epitaxial region connecting the set of full fins and the set of partial fins.

15. A method for fabricating a contact resistance test device, comprising:

forming a set of full fins;

cutting a subset of the set of full fins to form a set of partial fins;

forming a gate structure over the set of full fins and set of partial fins;

epitaxially growing a source region over a first end of the set of full fins and the set of partial fins and forming a drain region over a second end of the set of full fins, the set of partial fins being electrically isolated from the drain region;

forming an interlevel dielectric (ILD) layer over the source region and the drain region; etching contact holes in the ILD layer and into the source region and the drain region; and

forming a source contact to the first end of the set of full fins, a drain contact to the second end of the set of full fins and a probe contact to the first end of the set of partial fins for measuring contact resistance between the source contact and the drain contact.

16. The method as recited in claim 15 , wherein the probe contact includes an equal potential with the source region, the method further comprising measuring the contact resistance for devices formed by the set of full fins.

17. The method as recited in claim 15 , wherein etching contact holes includes etching the source region to provide an interface for the source contact and the probe contact.

18. The method as recited in claim 15 , forming a shallow trench isolation region at a base of the set of full fins and the set of partial fins.

19. The method as recited in claim 15 , wherein a conductor of the gate structure is formed over free edges of the set of partial fins.

20. The method as recited in claim 15 , wherein a voltage measured between the probe contact and the source contact measures contact resistance when a drain-to-source current is flowing in the set of full fins.