METHOD TO MAKE GATE-TO-BODY CONTACT TO RELEASE PLASMA INDUCED CHARGING
Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming plural fins on a substrate, with a STI region between adjacent fins; forming a dummy gate stack over and perpendicular to the fins, the gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of the dummy gate stack; forming source/drain regions at opposite sides of the dummy gate stack; forming an ILD over the STI regions between fins; removing the dummy gate stack forming a gate cavity; forming a gate dielectric in the gate cavity; removing the gate dielectric from the gate cavity in a protection diode area, exposing an underlying fin; implanting a dopant into the exposed fin; and forming a RMG in the gate cavity, wherein a protection diode is formed in the protection diode area.
1 . A device comprising:
a silicon substrate;
adjacent first and second silicon fins formed on the substrate;
shallow trench isolation (STI) regions formed between the adjacent first and second fins;
a metal gate formed over and perpendicular to the first and second fins;
source/drain regions formed on the first and second fins at opposite sides of the metal gate; and
a protection diode comprising the metal gate over the second fin.
2 . The device according to claim 1 , wherein the substrate comprises a p-type substrate, the source/drain regions on the second fin comprise n-type regions, the device further comprising an n-well under the metal gate over the second fin and under the source/drain regions on the second fin.
3 . The device according to claim 1 , wherein the substrate comprises a p-type substrate, and the source/drain regions on the second fin comprise p-type regions.
4 . The device according to claim 1 , further comprising a gate dielectric between the metal gate and the first fins, but no gate dielectric between the metal gate and the second fin, and the second fin is implanted with phosphorus (P) or arsenic (As) or is implanted with boron (B) or boron fluoride (BF 2 ).
5 . The device according to claim 1 , wherein metal gate comprises a work function metal on the sidewalls and bottom surface of the metal gate,
6 . The device according to claim 5 , further comprising a merged source/drain and gate contact in contact with the workflow metal on the sidewalls and with a top surface of the metal gate.
7 . The device according to claim 1 , further comprising:
an interlayer dielectric (ILD) over the metal gate, first and second silicon fins, and source/drain regions;
a metal 1 layer over the ILD; and
a second protection diode electrically connected to the metal 1 layer.
8 . A device comprising:
first and second fins formed on a substrate, with a shallow trench isolation (STI) region formed between the first and second fins;
a metal gate formed over and perpendicular to the first and second fins, the metal gate including sidewall spacers on opposite sides of the metal gate and source/drain regions at opposite sides of the metal gate;
a protection diode comprising the metal gate over the second fin;
an interlayer dielectric (ILD) formed over the STI regions between first and second fins; and
a metal 1 layer formed over the ILD.
9 . The device according to claim 8 , wherein the protection diode includes a dopant implanted in the second fin.
10 . The device according to claim 9 , wherein the dopant comprises phosphorus (P), arsenic (As), boron (B), or boron fluoride (BF 2 ).
11 . The device according to claim 8 , wherein the metal gate comprises a replacement metal gate (RMG).
12 . The device according to claim 8 , further comprising a second protection diode electrically connected to the metal 1 layer.
13 . The device according to claim 8 , wherein the substrate comprises a p-type substrate, the source/drain regions on the second fin comprise n-type regions
14 . The device according to claim 13 , further comprising an n-well under the metal gate over the second fin and under the source/drain regions on the second fin.
15 . The device according to claim 8 , wherein the substrate comprises a p-type substrate, and the source/drain regions on the second fin comprise p-type regions.
16 . The device according to claim 8 , further comprising a gate dielectric between the metal gate and the first fins, but no gate dielectric between the metal gate and the second fin, and the second fin is implanted with phosphorus (P) or arsenic (As) or is implanted with boron (B) or boron fluoride (BF 2 ).
17 . The device according to claim 17 , wherein metal gate comprises a work function metal on the sidewalls and bottom surface of the metal gate,
18 . The device according to claim 17 , further comprising a merged source/drain and gate contact in contact with the workflow metal on the sidewalls and with a top surface of the metal gate.
19 . A device comprising:
first and second fins formed on a substrate, with a shallow trench isolation (STI) region formed between the first and second fins;
a metal gate formed over and perpendicular to the first and second fins, the metal gate including sidewall spacers on opposite sides of the metal gate and source/drain regions at opposite sides of the metal gate;
a first protection diode comprising the metal gate over the second fin
an interlayer dielectric (ILD) formed over the STI regions between first and second fins;
a metal 1 layer formed over the ILD; and
a second protection diode electrically connected to the metal 1 layer.
20 . The device according to claim 19 , further comprising a gate dielectric between the metal gate and the first fins, but no gate dielectric between the metal gate and the second fin, and the second fin is implanted with phosphorus (P) or arsenic (As) or is implanted with boron (B) or boron fluoride (BF 2 ).