Vertical field effect transistors with metallic source/drain regions

1. A semiconductor device, comprising:

a first source/drain region formed on a semiconductor substrate;

a vertical semiconductor fin formed on the first source/drain region;

a second source/drain region formed on an upper surface of the vertical semiconductor fin;

a gate structure formed on a sidewall surface of the vertical semiconductor fin; and

a layer of insulating material encapsulating the vertical semiconductor fin and the gate structure;

wherein the first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer.

2. The semiconductor device of claim 1 , wherein the metallic layer of the first source/drain region extends along an entire length of the vertical semiconductor fin.

3. The semiconductor device of claim 1 , wherein the metallic layer comprises a metal-semiconductor alloy.

4. The semiconductor device of claim 3 , wherein the metal-semiconductor alloy comprises a silicide.

5. The semiconductor device of claim 1 , wherein the first source/drain region comprises a second epitaxial semiconductor layer, wherein the metallic layer is disposed between the first and second epitaxial semiconductor layers.

6. The semiconductor device of claim 1 , wherein the vertical semiconductor fin comprises an epitaxial semiconductor material that is epitaxially grown on the first epitaxial semiconductor layer of the first source/drain region.

7. The semiconductor device of claim 1 , further comprising at least a first vertical contact and a second vertical contact formed through the layer of insulating material and in contact with the metallic layer of the first source/drain region, wherein the first vertical contact is disposed adjacent to an end of the vertical semiconductor fin, and wherein the second vertical contact is disposed adjacent to a sidewall of the vertical semiconductor fin.

8. A method for fabricating a semiconductor device, comprising:

forming a first source/drain region on a semiconductor substrate, wherein the first source/drain region comprises a first epitaxial semiconductor layer and a sacrificial epitaxial semiconductor layer;

forming a vertical semiconductor fin on the first source/drain region;

forming a gate structure on a sidewall surface of the vertical semiconductor fin;

encapsulating the vertical semiconductor fin and the gate structure in insulating material;

forming a second source/drain region on an upper surface of the vertical semiconductor fin;

forming an opening through the insulating material and into the first source/drain region to expose the sacrificial epitaxial semiconductor layer of the first source/drain region;

removing at least a portion of the sacrificial epitaxial semiconductor layer through the opening in the insulating material to form a void in the first source/drain region;

filling the void in the first source/drain region with a metallic layer;

filling the opening with a conductive material to form a first vertical contact to the metallic layer of the first source/drain region.

9. The method of claim 8 , wherein forming the first source/drain region on the semiconductor substrate comprises forming a heteroepitaxial stack structure comprising the sacrificial epitaxial semiconductor layer disposed between the first epitaxial semiconductor layer and a second semiconductor epitaxial layer.

10. The method of claim 8 , wherein forming a vertical semiconductor fin on the first source/drain region comprises epitaxially growing the vertical semiconductor fin on the first epitaxial semiconductor layer of the first source/drain region.

11. The method of claim 8 , wherein removing at least a portion of the sacrificial epitaxial semiconductor layer to form a void in the first source/drain region comprises etching the sacrificial epitaxial semiconductor layer selective to the first epitaxial semiconductor layer.

12. The method of claim 8 , wherein filling the void in the first source/drain region with a metallic layer comprises:

depositing a layer of metallic material to fill the void with the metallic material;

performing a thermal anneal process to induce a reaction between the metallic material in the void and epitaxial semiconductor material of the first epitaxial semiconductor layer to form a metal-semiconductor alloy region within the first source/drain region; and

removing unreacted portions of the layer of metallic material.

13. The method of claim 12 , wherein the metal-semiconductor alloy region comprises a silicide.

14. The method of claim 8 , wherein forming an opening through the insulating material comprises forming two or more openings through the insulating material and into the first source/drain region to expose the sacrificial epitaxial semiconductor layer of the first source/drain region; and

wherein filling the opening with a conductive material comprises filling the two or more openings with the conductive material to form the first vertical contact and at least a second vertical contact to the metallic layer of the first source/drain region wherein the first vertical contact is disposed adjacent to an end of the vertical semiconductor fin, and wherein the second vertical contact is disposed adjacent to a sidewall of the vertical semiconductor fin.