Method and system of synchronizing processors to the same computational point
View Patent ↗A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.
1. A method for synchronizing central processing units (CPU) comprising:
generating, by a first processor, a first synchronization message when a first CPU reaches a synchronization point within a first series of instructions;
generating, by a second processor, a second synchronization message when a second CPU reaches the synchronization point within a second series of instructions, wherein the first and second series of instructions are identical;
communicating, by the first processor, the first synchronization message to the second processor;
communicating, by the second processor, the second synchronization message to the first processor;
determining, by the first processor, whether the second synchronization message was communicated;
determining, by the second processor, whether the first synchronization message was communicated; and
determining, by one of the first processor or the second processor, whether to execute a plurality of identical tasks in the respective first and second series of instructions based on whether the respective second or the first synchronization messages have been received by the one of the first processor or the second processor and whether the first and second synchronization messages are identical.
2. The method of claim 1 further comprising incrementing a synchronization counter in response to not receiving at least one of the first and second synchronization messages.
3. The method of claim 2 further comprising selectively determining whether to restart a first CPU and a second CPU in response to the synchronization counter being greater than a predetermined threshold.
4. The method of claim 1 further comprising determining whether the first CPU and the second CPU are synchronized based on a comparison of the first and second synchronization messages.
5. The method of claim 4 further comprising determining whether the first CPU and the second CPU are synchronized when the first synchronization message is generated and the second synchronization message is received.
6. The method of claim 5 further comprising generating a first processor synchronization signal in response to the determination that the first CPU and the second CPU are synchronized.
7. The method of claim 4 further comprising determining whether the first CPU and the second CPU are synchronized when the second synchronization message is generated and the first synchronization message is received.
8. The method of claim 7 further comprising generating a second processor synchronization signal in response to the determination that the first CPU and the second CPU are synchronized.
9. The method of claim 8 further comprising executing the plurality of tasks in response to receiving the first processor synchronization signal and the second synchronization signal.
10. The method of claim 8 further comprising not executing the plurality of tasks in response to not receiving at least one of the first and second synchronization signals.
11. A method for synchronizing central processing units (CPU) comprising:
generating, by a first processor, a first synchronization message when a first CPU reaches a synchronization point within a first series of instructions;
generating, by a second processor, a second synchronization message when a second CPU reaches the synchronization point within a second series of instructions, wherein the first and second series of instructions are identical;
communicating, by the first processor, the first synchronization message to the second processor;
communicating, by the second processor, the second synchronization message to the first processor;
determining, by the first processor, whether the second synchronization message was communicated;
determining, by the second processor, whether the first synchronization message was communicated; and
determining, by one of the first processor or the second processor, whether to execute at the same time a plurality of identical tasks in the respective first and second series of instructions based on at least one of:
whether the respective second or the first synchronization messages have been received by the one of the first processor or the second processor, or
a comparison of the first and second synchronization messages and whether the first and second synchronization messages are identical.
12. The method of claim 11 further comprising incrementing a synchronization counter in response to not receiving at least one of the first and second synchronization messages.
13. The method of claim 12 further comprising selectively determining whether to restart a first CPU and a second CPU in response to the synchronization counter being greater than a predetermined threshold.
14. The method of claim 11 further comprising determining whether the first CPU and the second CPU are synchronized based on the comparison of the first and second synchronization messages.
15. The method of claim 14 further comprising determining whether the first CPU and the second CPU are synchronized when the first synchronization message is generated and the second synchronization message is received.
16. The method of claim 15 further comprising generating a first processor synchronization signal in response to the determination that the first CPU and the second CPU are synchronized.
17. The method of claim 14 further comprising determining whether the first CPU and the second CPU are synchronized when the second synchronization message is generated and the first synchronization message is received.
18. The method of claim 17 further comprising generating a second processor synchronization signal in response to the determination that the first CPU and the second CPU are synchronized.
19. The method of claim 18 further comprising executing the plurality of tasks in response to receiving the first processor synchronization signal and the second synchronization signal.
20. The method of claim 18 further comprising not executing the plurality of tasks in response to not receiving at least one of the first and second synchronization signals.
21. A method for synchronizing central processing units (CPU) comprising:
generating a first memory address to a first memory register when a first CPU reaches a synchronization point;
generating a second memory address to a second memory register when a second CPU reaches the synchronization point;
comparing, in the first CPU, the first memory register to the second memory register and storing a result of the comparison in a third memory register;
comparing, in the second CPU, the first memory register to the second memory register and storing a result of the comparison in a fourth memory register;
comparing the third and fourth memory registers; and
determining whether to execute at the same time a plurality of identical tasks based on the result of the comparison between the third and fourth memory registers.
22. The method of claim 21 further comprising determining whether the first CPU and the second CPU are synchronized based on the comparison between the third and fourth memory registers.
23. The method of claim 22 further comprising determining the first CPU and the second CPU are synchronized when the third and fourth memory registers are identical.
24. The method of claim 23 further comprising generating a first processor synchronization signal in response to determining that the first CPU and the second CPU are synchronized.
25. The method of claim 24 further comprising generating a second processor synchronization signal in response to determining that the first CPU and the second CPU are synchronized.