IP Library Granted Patent US 9,768,185
Granted Patent B2
US 9,768,185 · App. 15/151,846 · Granted Sep 19, 2017

Non-volatile semiconductor memory device and manufacturing method thereof

Inventors: Yoshihiro Akutsu (Yokkaichi, JP); Ryota Katsumata (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11556H01L21/743H01L21/76889H01L23/535H01L27/1157H01L27/11573H01L27/11578H01L27/11582H01L2924/0002
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Quick Facts
Patent No.
US 9,768,185
App. No.
15/151,846
Granted
Sep 19, 2017
Kind
B2
Abstract

This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Claims (13)

1. A semiconductor memory device comprising:

an insulating layer;

a conductive layer provided above the insulating layer, the conductive layer having a first film and a second film provided on an upper part of the first film, the first film including silicon and metal;

a stacked body provided above the conductive layer and including a plurality of electrode layers separately stacked in a first direction;

a first semiconductor body provided in the stacked body and extending in the first direction, the first semiconductor body being electrically connected to the conductive layer, the second film being provided between the first semiconductor body and the first film;

a memory portion provided between the first semiconductor body and one of the plurality of electrode layers; and

a source layer extending in the first direction and in contact with the conductive layer.

2. The device according to claim 1 , wherein the second film includes silicon and impurity.

3. The device according to claim 1 , wherein the first film is a silicide layer of the silicon and the metal.

4. The device according to claim 1 , wherein the metal is Ni or Co.

5. The device according to claim 2 , wherein the impurity is boron.

6. The device according to claim 1 , further comprising an isolation layer extending in the first direction, the isolation layer being in contact with the first film.

7. The device according to claim 1 , wherein the source layer is in contact with the first film.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043541/0381 →
Continuity (3)
Continuation 14645793 · Mar 12, 2015
Provisional Application 62049017 · Sep 11, 2014
Related Publication 20160254271A1 · Sep 1, 2016